@@ -84,10 +84,6 @@ struct SpaprPhbState {
bool pcie_ecs; /* Allow access to PCIe extended config space? */
/* Fields for migration compatibility hacks */
- bool pre_2_8_migration;
- uint32_t mig_liobn;
- hwaddr mig_mem_win_addr, mig_mem_win_size;
- hwaddr mig_io_win_addr, mig_io_win_size;
bool pre_5_1_assoc;
};
@@ -1456,11 +1456,6 @@ struct ArchCPU {
opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
/* Fields related to migration compatibility hacks */
- bool pre_2_8_migration;
- target_ulong mig_msr_mask;
- uint64_t mig_insns_flags;
- uint64_t mig_insns_flags2;
- uint32_t mig_nb_BATs;
bool pre_2_10_migration;
bool pre_3_0_migration;
int32_t mig_slb_nr;
@@ -5222,81 +5222,6 @@ static void spapr_machine_2_8_class_options(MachineClass *mc)
DEFINE_SPAPR_MACHINE(2, 8);
-/*
- * pseries-2.7
- */
-
-static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
- uint64_t *buid, hwaddr *pio,
- hwaddr *mmio32, hwaddr *mmio64,
- unsigned n_dma, uint32_t *liobns, Error **errp)
-{
- /* Legacy PHB placement for pseries-2.7 and earlier machine types */
- const uint64_t base_buid = 0x800000020000000ULL;
- const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
- const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
- const hwaddr pio_offset = 0x80000000; /* 2 GiB */
- const uint32_t max_index = 255;
- const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
-
- uint64_t ram_top = MACHINE(spapr)->ram_size;
- hwaddr phb0_base, phb_base;
- int i;
-
- /* Do we have device memory? */
- if (MACHINE(spapr)->device_memory) {
- /* Can't just use maxram_size, because there may be an
- * alignment gap between normal and device memory regions
- */
- ram_top = MACHINE(spapr)->device_memory->base +
- memory_region_size(&MACHINE(spapr)->device_memory->mr);
- }
-
- phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
-
- if (index > max_index) {
- error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
- max_index);
- return false;
- }
-
- *buid = base_buid + index;
- for (i = 0; i < n_dma; ++i) {
- liobns[i] = SPAPR_PCI_LIOBN(index, i);
- }
-
- phb_base = phb0_base + index * phb_spacing;
- *pio = phb_base + pio_offset;
- *mmio32 = phb_base + mmio_offset;
- /*
- * We don't set the 64-bit MMIO window, relying on the PHB's
- * fallback behaviour of automatically splitting a large "32-bit"
- * window into contiguous 32-bit and 64-bit windows
- */
-
- return true;
-}
-
-static void spapr_machine_2_7_class_options(MachineClass *mc)
-{
- SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
- static GlobalProperty compat[] = {
- { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", },
- { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", },
- { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", },
- { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", },
- };
-
- spapr_machine_2_8_class_options(mc);
- mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
- mc->default_machine_opts = "modern-hotplug-events=off";
- compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
- compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
- smc->phb_placement = phb_placement_2_7;
-}
-
-DEFINE_SPAPR_MACHINE(2, 7);
-
static void spapr_machine_register_types(void)
{
type_register_static(&spapr_machine_info);
@@ -2101,8 +2101,6 @@ static Property spapr_phb_properties[] = {
(1ULL << 12) | (1ULL << 16)
| (1ULL << 21) | (1ULL << 24)),
DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1),
- DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState,
- pre_2_8_migration, false),
DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState,
pcie_ecs, true),
DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState,
@@ -2140,20 +2138,6 @@ static int spapr_pci_pre_save(void *opaque)
gpointer key, value;
int i;
- if (sphb->pre_2_8_migration) {
- sphb->mig_liobn = sphb->dma_liobn[0];
- sphb->mig_mem_win_addr = sphb->mem_win_addr;
- sphb->mig_mem_win_size = sphb->mem_win_size;
- sphb->mig_io_win_addr = sphb->io_win_addr;
- sphb->mig_io_win_size = sphb->io_win_size;
-
- if ((sphb->mem64_win_size != 0)
- && (sphb->mem64_win_addr
- == (sphb->mem_win_addr + sphb->mem_win_size))) {
- sphb->mig_mem_win_size += sphb->mem64_win_size;
- }
- }
-
g_free(sphb->msi_devs);
sphb->msi_devs = NULL;
sphb->msi_devs_num = g_hash_table_size(sphb->msi);
@@ -2200,13 +2184,6 @@ static int spapr_pci_post_load(void *opaque, int version_id)
return 0;
}
-static bool pre_2_8_migration(void *opaque, int version_id)
-{
- SpaprPhbState *sphb = opaque;
-
- return sphb->pre_2_8_migration;
-}
-
static const VMStateDescription vmstate_spapr_pci = {
.name = "spapr_pci",
.version_id = 2,
@@ -2216,11 +2193,6 @@ static const VMStateDescription vmstate_spapr_pci = {
.post_load = spapr_pci_post_load,
.fields = (const VMStateField[]) {
VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL),
- VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration),
- VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration),
- VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration),
- VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration),
- VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration),
VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0,
vmstate_spapr_pci_lsi, SpaprPciLsi),
VMSTATE_INT32(msi_devs_num, SpaprPhbState),
@@ -7452,7 +7452,6 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
}
static Property ppc_cpu_properties[] = {
- DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
false),
DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
@@ -118,13 +118,6 @@ static const VMStateInfo vmstate_info_vsr = {
#define VMSTATE_VSR_ARRAY(_f, _s, _n) \
VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0)
-static bool cpu_pre_2_8_migration(void *opaque, int version_id)
-{
- PowerPCCPU *cpu = opaque;
-
- return cpu->pre_2_8_migration;
-}
-
#if defined(TARGET_PPC64)
static bool cpu_pre_3_0_migration(void *opaque, int version_id)
{
@@ -139,22 +132,6 @@ static int cpu_pre_save(void *opaque)
PowerPCCPU *cpu = opaque;
CPUPPCState *env = &cpu->env;
int i;
- uint64_t insns_compat_mask =
- PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB
- | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES
- | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES
- | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT
- | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ
- | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC
- | PPC_64B | PPC_64BX | PPC_ALTIVEC
- | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD;
- uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX
- | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206
- | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
- | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
- | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
- | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM
- | PPC2_MEM_LWSYNC;
env->spr[SPR_LR] = env->lr;
env->spr[SPR_CTR] = env->ctr;
@@ -177,29 +154,6 @@ static int cpu_pre_save(void *opaque)
env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4];
}
- /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
- if (cpu->pre_2_8_migration) {
- /*
- * Mask out bits that got added to msr_mask since the versions
- * which stupidly included it in the migration stream.
- */
- target_ulong metamask = 0
-#if defined(TARGET_PPC64)
- | (1ULL << MSR_TS0)
- | (1ULL << MSR_TS1)
-#endif
- ;
- cpu->mig_msr_mask = env->msr_mask & ~metamask;
- cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
- /*
- * CPU models supported by old machines all have
- * PPC_MEM_TLBIE, so we set it unconditionally to allow
- * backward migration from a POWER9 host to a POWER8 host.
- */
- cpu->mig_insns_flags |= PPC_MEM_TLBIE;
- cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
- cpu->mig_nb_BATs = env->nb_BATs;
- }
if (cpu->pre_3_0_migration) {
if (cpu->hash64_opts) {
cpu->mig_slb_nr = cpu->hash64_opts->slb_size;
@@ -760,12 +714,6 @@ const VMStateDescription vmstate_ppc_cpu = {
/* Backward compatible internal state */
VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU),
- /* Sanity checking */
- VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
- VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
- VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
- cpu_pre_2_8_migration),
- VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * const []) {
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.7 specific code with this patch for now. While at it, also remove pre-2.8-migration hacks introduced for backward migration compatibility. Suggested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> --- include/hw/pci-host/spapr.h | 4 -- target/ppc/cpu.h | 5 --- hw/ppc/spapr.c | 75 ------------------------------------- hw/ppc/spapr_pci.c | 28 -------------- target/ppc/cpu_init.c | 1 - target/ppc/machine.c | 52 ------------------------- 6 files changed, 165 deletions(-)