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[88.28.18.183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd574282esm8469346f8f.104.2024.09.30.02.12.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:12:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold() Date: Mon, 30 Sep 2024 11:11:00 +0200 Message-ID: <20240930091101.40591-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since all code creating vCPUs now set the 'cpu-big-endian' property, we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold(): the CP0C0_BE bit is set using the property cpu->is_big_endian value. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 02e2e72f2d..9724e71a5e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -202,9 +202,6 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) env->CP0_PRid = env->cpu_model->CP0_PRid; env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, CP0C0_BE, 1, cpu->is_big_endian); -#if TARGET_BIG_ENDIAN - env->CP0_Config0 |= (1 << CP0C0_BE); -#endif env->CP0_Config1 = env->cpu_model->CP0_Config1; env->CP0_Config2 = env->cpu_model->CP0_Config2; env->CP0_Config3 = env->cpu_model->CP0_Config3;