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envelope-from=debug@rivosinc.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Execution environment config CSR controlling user env and current privilege state shouldn't be limited to qemu-system only. *envcfg CSRs control enabling of features in next lesser mode. In some cases bits *envcfg CSR can be lit up by kernel as part of kernel policy or software (user app) can choose to opt-in by issuing a system call (e.g. prctl). In case of qemu-user, it should be no different because qemu is providing underlying execution environment facility and thus either should provide some default value in *envcfg CSRs or react to system calls (prctls) initiated from application. priv is set to PRV_U and menvcfg/senvcfg set to 0 for qemu-user on reest. `henvcfg` has been left for qemu-system only because it is not expected that someone will use qemu-user where application is expected to have hypervisor underneath which is controlling its execution environment. If such a need arises then `henvcfg` could be exposed as well. Relevant discussion: https://lore.kernel.org/all/CAKmqyKOTVWPFep2msTQVdUmJErkH+bqCcKEQ4hAnyDFPdWKe0Q@mail.gmail.com/ Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 9 +++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cb675f0278..3538c2ae2e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1024,7 +1024,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) } pmp_unlock_entries(env); +#else + env->priv = PRV_U; + env->senvcfg = 0; + env->menvcfg = 0; #endif + env->xl = riscv_cpu_mxl(env); riscv_cpu_update_mask(env); cs->exception_index = RISCV_EXCP_NONE; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1619c3acb6..2623f6cf75 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -234,8 +234,12 @@ struct CPUArchState { uint32_t elf_flags; #endif -#ifndef CONFIG_USER_ONLY target_ulong priv; + /* CSRs for execution environment configuration */ + uint64_t menvcfg; + target_ulong senvcfg; + +#ifndef CONFIG_USER_ONLY /* This contains QEMU specific information about the virt state. */ bool virt_enabled; target_ulong geilen; @@ -445,12 +449,9 @@ struct CPUArchState { target_ulong upmmask; target_ulong upmbase; - /* CSRs for execution environment configuration */ - uint64_t menvcfg; uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; uint64_t sstateen[SMSTATEEN_MAX_COUNT]; - target_ulong senvcfg; uint64_t henvcfg; #endif target_ulong cur_pmmask;