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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20710e11e02sm36539875ad.14.2024.09.09.10.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 10:28:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, daniel@0x0f.com Subject: [PATCH v3 20/26] target/m68k: Move gen_addr_fault into gen_{load, store}_mode_fp Date: Mon, 9 Sep 2024 10:28:17 -0700 Message-ID: <20240909172823.649837-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240909172823.649837-1-richard.henderson@linaro.org> References: <20240909172823.649837-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Move the exception to be raised into the helpers. This in preparation for raising other exceptions, and still wanting to return failure. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/m68k/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c81d093c61..df886ed062 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1023,6 +1023,7 @@ static bool gen_load_mode_fp(DisasContext *s, uint16_t insn, int opsize, return true; case 1: /* Address register direct. */ + gen_addr_fault(s); return false; case 7: /* Other */ @@ -1079,6 +1080,7 @@ static bool gen_load_mode_fp(DisasContext *s, uint16_t insn, int opsize, case 6: /* Indirect index + displacement. */ addr = gen_lea_mode(s, mode, reg0, opsize); if (IS_NULL_QREG(addr)) { + gen_addr_fault(s); return false; } gen_load_fp(s, opsize, addr, fp, index); @@ -1112,6 +1114,7 @@ static bool gen_store_mode_fp(DisasContext *s, uint16_t insn, int opsize, return true; case 1: /* Address register direct. */ + gen_addr_fault(s); return false; case 2: /* Indirect register */ @@ -1122,6 +1125,7 @@ static bool gen_store_mode_fp(DisasContext *s, uint16_t insn, int opsize, case 7: /* Other */ addr = gen_lea_mode(s, mode, reg0, opsize); if (IS_NULL_QREG(addr)) { + gen_addr_fault(s); return false; } gen_store_fp(s, opsize, addr, fp, index); @@ -4887,10 +4891,9 @@ DISAS_INSN(fpu) case 3: /* fmove out */ cpu_src = gen_fp_ptr(REG(ext, 7)); opsize = ext_opsize(ext, 10); - if (!gen_store_mode_fp(s, insn, opsize, cpu_src, IS_USER(s))) { - gen_addr_fault(s); + if (gen_store_mode_fp(s, insn, opsize, cpu_src, IS_USER(s))) { + gen_helper_update_fpsr(tcg_env, cpu_src); } - gen_helper_update_fpsr(tcg_env, cpu_src); return; case 4: /* fmove to control register. */ case 5: /* fmove from control register. */ @@ -4909,7 +4912,6 @@ DISAS_INSN(fpu) opsize = ext_opsize(ext, 10); cpu_src = gen_fp_result_ptr(); if (!gen_load_mode_fp(s, insn, opsize, cpu_src, IS_USER(s))) { - gen_addr_fault(s); return; } } else {