| Message ID | 20240830061607.1940-15-zhiwei_liu@linux.alibaba.com |
|---|---|
| State | New |
| Headers | show |
| Series | tcg/riscv: Add support for vector | expand |
On 8/29/24 23:16, LIU Zhiwei wrote: > From: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com> > > Signed-off-by: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com> > Reviewed-by: Liu Zhiwei<zhiwei_liu@linux.alibaba.com> > --- > tcg/riscv/tcg-target.h | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index eb5129a976..b8f553207e 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -143,9 +143,11 @@ typedef enum { #define TCG_TARGET_HAS_tst 0 /* vector instructions */ -#define TCG_TARGET_HAS_v64 0 -#define TCG_TARGET_HAS_v128 0 -#define TCG_TARGET_HAS_v256 0 +#define have_rvv (cpuinfo & CPUINFO_ZVE64X) + +#define TCG_TARGET_HAS_v64 have_rvv +#define TCG_TARGET_HAS_v128 have_rvv +#define TCG_TARGET_HAS_v256 have_rvv #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_nand_vec 0