diff mbox series

[09/11,v2] target/riscv: Update interrupt return in CLIC mode

Message ID 20240819160742.27586-13-Ian.Brockbank@cirrus.com
State New
Headers show
Series RISC-V: support CLIC v0.9 specification | expand

Commit Message

Ian Brockbank Aug. 19, 2024, 4:02 p.m. UTC 
From: Ian Brockbank <ian.brockbank@cirrus.com>

When a vectored interrupt is selected and serviced, the hardware will
automatically clear the corresponding pending bit in edge-triggered mode.
This may lead to a lower privilege interrupt pending forever.

Therefore when interrupts return, pull a pending interrupt to service.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Ian Brockbank <ian.brockbank@cirrus.com>
---
 target/riscv/op_helper.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

--
2.46.0.windows.1
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diff mbox series

Patch

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 25a5263573..b6ca3ad598 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -25,7 +25,11 @@ 
 #include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"

-/* Exceptions processing helpers */
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/riscv_clic.h"
+#endif
+
+/* Exception processing helpers */
 G_NORETURN void riscv_raise_exception(CPURISCVState *env,
                                       uint32_t exception, uintptr_t pc)
 {
@@ -259,6 +263,7 @@  void helper_cbo_inval(CPURISCVState *env, target_ulong address)

 #ifndef CONFIG_USER_ONLY

+/* Return from PRV_S interrupt */
 target_ulong helper_sret(CPURISCVState *env)
 {
     uint64_t mstatus;
@@ -292,8 +297,17 @@  target_ulong helper_sret(CPURISCVState *env)
     }
     env->mstatus = mstatus;

+    if (riscv_clic_is_clic_mode(env)) {
+        /* Update mintstatus with the PRV_S information */
+        target_ulong spil = get_field(env->scause, SCAUSE_SPIL);
+        env->mintstatus = set_field(env->mintstatus, MINTSTATUS_SIL, spil);
+        env->scause = set_field(env->scause, SCAUSE_SPIE, 1);
+        env->scause = set_field(env->scause, SCAUSE_SPP, PRV_U);
+        riscv_clic_get_next_interrupt(env->clic);
+    }
+
     if (riscv_has_ext(env, RVH) && !env->virt_enabled) {
-        /* We support Hypervisor extensions and virtulisation is disabled */
+        /* We support Hypervisor extensions and virtualization is disabled */
         target_ulong hstatus = env->hstatus;

         prev_virt = get_field(hstatus, HSTATUS_SPV);
@@ -312,6 +326,7 @@  target_ulong helper_sret(CPURISCVState *env)
     return retpc;
 }

+/* Return from PRV_M interrupt */
 target_ulong helper_mret(CPURISCVState *env)
 {
     if (!(env->priv >= PRV_M)) {
@@ -344,6 +359,16 @@  target_ulong helper_mret(CPURISCVState *env)
     }
     env->mstatus = mstatus;

+    if (riscv_clic_is_clic_mode(env)) {
+        /* Update mintstatus with the PRV_M information */
+        target_ulong mpil = get_field(env->mcause, MCAUSE_MPIL);
+        env->mintstatus = set_field(env->mintstatus, MINTSTATUS_MIL, mpil);
+        env->mcause = set_field(env->mcause, MCAUSE_MPIE, 1);
+        env->mcause = set_field(env->mcause, MCAUSE_MPP,
+                                riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
+        riscv_clic_get_next_interrupt(env->clic);
+    }
+
     if (riscv_has_ext(env, RVH) && prev_virt) {
         riscv_cpu_swap_hypervisor_regs(env);
     }