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Fri, 16 Aug 2024 19:06:50 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47GJ6mPl025080 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Aug 2024 19:06:48 GMT Received: from hu-bcain-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 16 Aug 2024 12:06:48 -0700 From: Brian Cain To: CC: , , , , , Laurent Vivier Subject: [PATCH 1/3] target/hexagon: Rename HEX_EXCP_ => HEX_EVENT_ Date: Fri, 16 Aug 2024 12:06:17 -0700 Message-ID: <20240816190620.1418311-1-bcain@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: cbGoIqboWp0iuNzGUzR_MLocQXeipuHK X-Proofpoint-ORIG-GUID: cbGoIqboWp0iuNzGUzR_MLocQXeipuHK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-16_13,2024-08-16_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 suspectscore=0 clxscore=1011 priorityscore=1501 malwarescore=0 impostorscore=0 mlxlogscore=500 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408160135 Received-SPF: pass client-ip=205.220.180.131; envelope-from=bcain@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Change the name of these definitions to reflect that they correspond to the event code for the exception. Signed-off-by: Brian Cain Reviewed-by: Taylor Simpson --- linux-user/hexagon/cpu_loop.c | 4 ++-- target/hexagon/cpu.h | 2 +- target/hexagon/cpu_bits.h | 14 +++++++------- target/hexagon/gen_tcg.h | 2 +- target/hexagon/translate.c | 6 +++--- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index d41159e52a..f9d9ae515f 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -42,7 +42,7 @@ void cpu_loop(CPUHexagonState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case HEX_EXCP_TRAP0: + case HEX_EVENT_TRAP0: syscallnum = env->gpr[6]; env->gpr[HEX_REG_PC] += 4; ret = do_syscall(env, @@ -60,7 +60,7 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] = ret; } break; - case HEX_EXCP_PC_NOT_ALIGNED: + case HEX_EVENT_PC_NOT_ALIGNED: force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, env->gpr[HEX_REG_R31]); break; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 764f3c38cc..3ef2e5bf4b 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -149,7 +149,7 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, } *flags = hex_flags; if (*pc & PCALIGN_MASK) { - hexagon_raise_exception_err(env, HEX_EXCP_PC_NOT_ALIGNED, 0); + hexagon_raise_exception_err(env, HEX_EVENT_PC_NOT_ALIGNED, 0); } } diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 4279281a71..5a71af2469 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -23,14 +23,14 @@ #define PCALIGN 4 #define PCALIGN_MASK (PCALIGN - 1) -#define HEX_EXCP_FETCH_NO_UPAGE 0x012 -#define HEX_EXCP_INVALID_PACKET 0x015 -#define HEX_EXCP_INVALID_OPCODE 0x015 -#define HEX_EXCP_PC_NOT_ALIGNED 0x01e -#define HEX_EXCP_PRIV_NO_UREAD 0x024 -#define HEX_EXCP_PRIV_NO_UWRITE 0x025 +#define HEX_EVENT_FETCH_NO_UPAGE 0x012 +#define HEX_EVENT_INVALID_PACKET 0x015 +#define HEX_EVENT_INVALID_OPCODE 0x015 +#define HEX_EVENT_PC_NOT_ALIGNED 0x01e +#define HEX_EVENT_PRIV_NO_UREAD 0x024 +#define HEX_EVENT_PRIV_NO_UWRITE 0x025 -#define HEX_EXCP_TRAP0 0x172 +#define HEX_EVENT_TRAP0 0x172 #define PACKET_WORDS_MAX 4 diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 3fc1f4e281..8a3b801287 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -1365,7 +1365,7 @@ do { \ uiV = uiV; \ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \ - TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \ + TCGv excp = tcg_constant_tl(HEX_EVENT_TRAP0); \ gen_helper_raise_exception(tcg_env, excp); \ } while (0) #endif diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 4b1bee3c6d..2f187c6ceb 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -591,7 +591,7 @@ static void gen_insn(DisasContext *ctx) ctx->insn->generate(ctx); mark_store_width(ctx); } else { - gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); + gen_exception_end_tb(ctx, HEX_EVENT_INVALID_OPCODE); } } @@ -968,7 +968,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) nwords = read_packet_words(env, ctx, words); if (!nwords) { - gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); + gen_exception_end_tb(ctx, HEX_EVENT_INVALID_PACKET); return; } @@ -984,7 +984,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) gen_commit_packet(ctx); ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; } else { - gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); + gen_exception_end_tb(ctx, HEX_EVENT_INVALID_PACKET); } }