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Tue, 13 Aug 2024 19:41:21 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 12/15] tcg/riscv: Implement vector min/max ops Date: Tue, 13 Aug 2024 19:34:33 +0800 Message-Id: <20240813113436.831-13-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.100; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-100.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 25 +++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 2 +- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index af21b4593c..c9c69d61fb 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -316,6 +316,11 @@ typedef enum { OPC_VSADDU_VV = 0x80000057 | V_OPIVV, OPC_VSSUBU_VV = 0x88000057 | V_OPIVV, + OPC_VMAX_VV = 0x1c000057 | V_OPIVV, + OPC_VMAXU_VV = 0x18000057 | V_OPIVV, + OPC_VMIN_VV = 0x14000057 | V_OPIVV, + OPC_VMINU_VV = 0x10000057 | V_OPIVV, + OPC_VMSEQ_VV = 0x60000057 | V_OPIVV, OPC_VMSEQ_VI = 0x60000057 | V_OPIVI, OPC_VMSEQ_VX = 0x60000057 | V_OPIVX, @@ -2342,6 +2347,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ussub_vec: tcg_out_opc_vv(s, OPC_VSSUBU_VV, a0, a1, a2, true); break; + case INDEX_op_smax_vec: + tcg_out_opc_vv(s, OPC_VMAX_VV, a0, a1, a2, true); + break; + case INDEX_op_smin_vec: + tcg_out_opc_vv(s, OPC_VMIN_VV, a0, a1, a2, true); + break; + case INDEX_op_umax_vec: + tcg_out_opc_vv(s, OPC_VMAXU_VV, a0, a1, a2, true); + break; + case INDEX_op_umin_vec: + tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true); + break; case INDEX_op_rvv_cmpcond_vec: { RISCVInsn op; @@ -2421,6 +2438,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return 1; case INDEX_op_cmp_vec: return -1; @@ -2587,6 +2608,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return C_O1_I2(v, v, v); case INDEX_op_cmp_vec: case INDEX_op_rvv_merge_vec: diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 21251f8b23..35e7086ad7 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -162,7 +162,7 @@ typedef enum { #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0