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[v1,10/15] tcg/riscv: Implement vector not/neg ops

Message ID 20240813113436.831-11-zhiwei_liu@linux.alibaba.com
State New
Headers show
Series tcg/riscv: Add support for vector | expand

Commit Message

LIU Zhiwei Aug. 13, 2024, 11:34 a.m. UTC 
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 tcg/riscv/tcg-target-con-set.h |  1 +
 tcg/riscv/tcg-target.c.inc     | 13 +++++++++++++
 tcg/riscv/tcg-target.h         |  4 ++--
 3 files changed, 16 insertions(+), 2 deletions(-)

Comments

Richard Henderson Aug. 14, 2024, 9:45 a.m. UTC | #1 
On 8/13/24 21:34, LIU Zhiwei wrote:
> @@ -2312,6 +2314,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
>       case INDEX_op_xor_vec:
>           tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true);
>           break;
> +    case INDEX_op_not_vec:
> +        tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);
> +        break;
> +    case INDEX_op_neg_vec:
> +        tcg_out_opc_vx(s, OPC_VRSUB_VX, a0, a1, TCG_REG_ZERO, true);
> +        break;

Any reason not to use vrsub.vi?  Not wrong, just surprising.

Obviously, NOT does not require SEW change.

r~
LIU Zhiwei Aug. 27, 2024, 7:55 a.m. UTC | #2 
On 2024/8/14 17:45, Richard Henderson wrote:
> On 8/13/24 21:34, LIU Zhiwei wrote:
>> @@ -2312,6 +2314,12 @@ static void tcg_out_vec_op(TCGContext *s, 
>> TCGOpcode opc,
>>       case INDEX_op_xor_vec:
>>           tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true);
>>           break;
>> +    case INDEX_op_not_vec:
>> +        tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);
>> +        break;
>> +    case INDEX_op_neg_vec:
>> +        tcg_out_opc_vx(s, OPC_VRSUB_VX, a0, a1, TCG_REG_ZERO, true);
>> +        break;
>
> Any reason not to use vrsub.vi?  Not wrong, just surprising.
We will use vrsub.vi.
>
> Obviously, NOT does not require SEW change.

OK.

Thanks,
Zhiwei

>
> r~
diff mbox series

Patch

diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
index 23b391dd07..781b18a09e 100644
--- a/tcg/riscv/tcg-target-con-set.h
+++ b/tcg/riscv/tcg-target-con-set.h
@@ -24,5 +24,6 @@  C_O2_I4(r, r, rZ, rZ, rM, rM)
 C_O0_I2(v, r)
 C_O0_I2(v, vK)
 C_O1_I1(v, r)
+C_O1_I1(v, v)
 C_O1_I2(v, v, v)
 C_O1_I2(v, v, vK)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 3f1e215e90..a33c634dbb 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -306,7 +306,9 @@  typedef enum {
     OPC_VAND_VV = 0x24000057 | V_OPIVV,
     OPC_VOR_VV = 0x28000057 | V_OPIVV,
     OPC_VXOR_VV = 0x2c000057 | V_OPIVV,
+    OPC_VXOR_VI = 0x2c000057 | V_OPIVI,
 
+    OPC_VRSUB_VX = 0xc000057 | V_OPIVX,
     OPC_VMSEQ_VV = 0x60000057 | V_OPIVV,
     OPC_VMSEQ_VI = 0x60000057 | V_OPIVI,
     OPC_VMSEQ_VX = 0x60000057 | V_OPIVX,
@@ -2312,6 +2314,12 @@  static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_xor_vec:
         tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true);
         break;
+    case INDEX_op_not_vec:
+        tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);
+        break;
+    case INDEX_op_neg_vec:
+        tcg_out_opc_vx(s, OPC_VRSUB_VX, a0, a1, TCG_REG_ZERO, true);
+        break;
     case INDEX_op_rvv_cmpcond_vec:
         {
             RISCVInsn op;
@@ -2384,6 +2392,8 @@  int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_and_vec:
     case INDEX_op_or_vec:
     case INDEX_op_xor_vec:
+    case INDEX_op_not_vec:
+    case INDEX_op_neg_vec:
         return 1;
     case INDEX_op_cmp_vec:
         return -1;
@@ -2537,6 +2547,9 @@  static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_dupm_vec:
     case INDEX_op_ld_vec:
         return C_O1_I1(v, r);
+    case INDEX_op_neg_vec:
+    case INDEX_op_not_vec:
+        return C_O1_I1(v, v);
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
     case INDEX_op_and_vec:
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 12a7a37aaa..401696d639 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -151,8 +151,8 @@  typedef enum {
 #define TCG_TARGET_HAS_nand_vec         0
 #define TCG_TARGET_HAS_nor_vec          0
 #define TCG_TARGET_HAS_eqv_vec          0
-#define TCG_TARGET_HAS_not_vec          0
-#define TCG_TARGET_HAS_neg_vec          0
+#define TCG_TARGET_HAS_not_vec          1
+#define TCG_TARGET_HAS_neg_vec          1
 #define TCG_TARGET_HAS_abs_vec          0
 #define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_rots_vec         0