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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bcb19csm544275866b.42.2024.08.06.05.52.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 05/28] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState Date: Tue, 6 Aug 2024 14:51:33 +0200 Message-ID: <20240806125157.91185-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philmd@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Bibo Mao It is easier to manage one array of MMIO MR rather than one per vCPU. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-6-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 2 +- hw/intc/loongson_ipi.c | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 70e00dc1a7..5a52dfbf4d 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; - MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; uint32_t set; @@ -39,6 +38,7 @@ struct LoongsonIPIClass { struct LoongsonIPIState { LoongsonIPICommonState parent_obj; + MemoryRegion *ipi_mmio_mem; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 7d15c28e94..03878b896f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } + s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); for (unsigned i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } @@ -338,6 +338,10 @@ static void loongson_ipi_common_unrealize(DeviceState *dev) static void loongson_ipi_unrealize(DeviceState *dev) { + LoongsonIPIState *s = LOONGSON_IPI(dev); + + g_free(s->ipi_mmio_mem); + loongson_ipi_common_unrealize(dev); }