diff mbox series

[10/18] bsd-user: Add RISC-V thread setup and initialization support

Message ID 20240802083423.142365-11-itachis@FreeBSD.org
State New
Headers show
Series bsd-user: Comprehensive RISCV support | expand

Commit Message

Ajeet Singh Aug. 2, 2024, 8:34 a.m. UTC
From: Mark Corbin <mark.corbin@embecsom.com>

Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers based on
the provided image information.

Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
---
 bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 bsd-user/riscv/target_arch_thread.h

Comments

Richard Henderson Aug. 2, 2024, 1:30 p.m. UTC | #1
On 8/2/24 18:34, Ajeet Singh wrote:
> From: Mark Corbin <mark.corbin@embecsom.com>
> 
> Implemented functions for setting up and initializing threads in the
> RISC-V architecture.
> The 'target_thread_set_upcall' function sets up the stack pointer,
> program counter, and function argument for new threads.
> The 'target_thread_init' function initializes thread registers based on
> the provided image information.
> 
> Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
> Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
> ---
>   bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++
>   1 file changed, 47 insertions(+)
>   create mode 100644 bsd-user/riscv/target_arch_thread.h
> 
> diff --git a/bsd-user/riscv/target_arch_thread.h b/bsd-user/riscv/target_arch_thread.h
> new file mode 100644
> index 0000000000..faabb9fb45
> --- /dev/null
> +++ b/bsd-user/riscv/target_arch_thread.h
> @@ -0,0 +1,47 @@
> +/*
> + *  RISC-V thread support
> + *
> + *  Copyright (c) 2019 Mark Corbin
> + *
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License as published by
> + *  the Free Software Foundation; either version 2 of the License, or
> + *  (at your option) any later version.
> + *
> + *  This program is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License
> + *  along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_THREAD_H
> +#define TARGET_ARCH_THREAD_H
> +
> +/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */
> +static inline void target_thread_set_upcall(CPURISCVState *regs,
> +    abi_ulong entry, abi_ulong arg, abi_ulong stack_base,
> +    abi_ulong stack_size)
> +{
> +    abi_ulong sp;
> +
> +    sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1);
> +
> +    regs->gpr[xSP] = sp;
> +    regs->pc = entry;
> +    regs->gpr[xA0] = arg;
> +}
> +
> +/* Compare with exec_setregs() in riscv/riscv/machdep.c */

exec_machdep.c.

> +static inline void target_thread_init(struct target_pt_regs *regs,
> +    struct image_info *infop)
> +{
> +    regs->sepc = infop->entry;
> +    regs->regs[xRA] = infop->entry;
> +    regs->regs[10] = infop->start_stack;               /* a0 */

xA0

> +    regs->regs[xSP] = infop->start_stack & ~(16 - 1);

ROUND_DOWN.


r~
Warner Losh Aug. 3, 2024, 12:05 a.m. UTC | #2
On Fri, Aug 2, 2024 at 7:30 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 8/2/24 18:34, Ajeet Singh wrote:
> > From: Mark Corbin <mark.corbin@embecsom.com>
> >
> > Implemented functions for setting up and initializing threads in the
> > RISC-V architecture.
> > The 'target_thread_set_upcall' function sets up the stack pointer,
> > program counter, and function argument for new threads.
> > The 'target_thread_init' function initializes thread registers based on
> > the provided image information.
> >
> > Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> > Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
> > Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
> > ---
> >   bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++
> >   1 file changed, 47 insertions(+)
> >   create mode 100644 bsd-user/riscv/target_arch_thread.h
> >
> > diff --git a/bsd-user/riscv/target_arch_thread.h
> b/bsd-user/riscv/target_arch_thread.h
> > new file mode 100644
> > index 0000000000..faabb9fb45
> > --- /dev/null
> > +++ b/bsd-user/riscv/target_arch_thread.h
> > @@ -0,0 +1,47 @@
> > +/*
> > + *  RISC-V thread support
> > + *
> > + *  Copyright (c) 2019 Mark Corbin
> > + *
> > + *  This program is free software; you can redistribute it and/or modify
> > + *  it under the terms of the GNU General Public License as published by
> > + *  the Free Software Foundation; either version 2 of the License, or
> > + *  (at your option) any later version.
> > + *
> > + *  This program is distributed in the hope that it will be useful,
> > + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *  GNU General Public License for more details.
> > + *
> > + *  You should have received a copy of the GNU General Public License
> > + *  along with this program; if not, see <http://www.gnu.org/licenses/
> >.
> > + */
> > +
> > +#ifndef TARGET_ARCH_THREAD_H
> > +#define TARGET_ARCH_THREAD_H
> > +
> > +/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */
> > +static inline void target_thread_set_upcall(CPURISCVState *regs,
> > +    abi_ulong entry, abi_ulong arg, abi_ulong stack_base,
> > +    abi_ulong stack_size)
> > +{
> > +    abi_ulong sp;
> > +
> > +    sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1);
> > +
> > +    regs->gpr[xSP] = sp;
> > +    regs->pc = entry;
> > +    regs->gpr[xA0] = arg;
> > +}
> > +
> > +/* Compare with exec_setregs() in riscv/riscv/machdep.c */
>
> exec_machdep.c.
>
> > +static inline void target_thread_init(struct target_pt_regs *regs,
> > +    struct image_info *infop)
> > +{
> > +    regs->sepc = infop->entry;
> > +    regs->regs[xRA] = infop->entry;
> > +    regs->regs[10] = infop->start_stack;               /* a0 */
>
> xA0
>
> > +    regs->regs[xSP] = infop->start_stack & ~(16 - 1);
>
> ROUND_DOWN.
>

Oh, I should do a pass through our tree for rounding like this to add this
macro.

Warner


>
> r~
>
diff mbox series

Patch

diff --git a/bsd-user/riscv/target_arch_thread.h b/bsd-user/riscv/target_arch_thread.h
new file mode 100644
index 0000000000..faabb9fb45
--- /dev/null
+++ b/bsd-user/riscv/target_arch_thread.h
@@ -0,0 +1,47 @@ 
+/*
+ *  RISC-V thread support
+ *
+ *  Copyright (c) 2019 Mark Corbin
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_THREAD_H
+#define TARGET_ARCH_THREAD_H
+
+/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */
+static inline void target_thread_set_upcall(CPURISCVState *regs,
+    abi_ulong entry, abi_ulong arg, abi_ulong stack_base,
+    abi_ulong stack_size)
+{
+    abi_ulong sp;
+
+    sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1);
+
+    regs->gpr[xSP] = sp;
+    regs->pc = entry;
+    regs->gpr[xA0] = arg;
+}
+
+/* Compare with exec_setregs() in riscv/riscv/machdep.c */
+static inline void target_thread_init(struct target_pt_regs *regs,
+    struct image_info *infop)
+{
+    regs->sepc = infop->entry;
+    regs->regs[xRA] = infop->entry;
+    regs->regs[10] = infop->start_stack;               /* a0 */
+    regs->regs[xSP] = infop->start_stack & ~(16 - 1);
+}
+
+#endif /* TARGET_ARCH_THREAD_H */