| Message ID | 20240801091332.49256-1-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [PATCH-for-9.1] hw/pci-host/gt64120: Set PCI base address register write mask | expand |
On Thu, Aug 01, 2024 at 11:13:32AM +0200, Philippe Mathieu-Daudé wrote: > When booting Linux we see: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) > > This is due to missing base address register write mask. > Add it to get: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] > pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] > pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] > pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] > pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] > pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] > > Mention the datasheet referenced. Remove the "Malta assumptions ahead" > comment since the reset values from the datasheet are used. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/pci-host/gt64120.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c > index e02efc9e2e..0b00e98e0a 100644 > --- a/hw/pci-host/gt64120.c > +++ b/hw/pci-host/gt64120.c > @@ -1,6 +1,8 @@ > /* > * QEMU GT64120 PCI host > * > + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) > + * > * Copyright (c) 2006,2007 Aurelien Jarno > * > * Permission is hereby granted, free of charge, to any person obtaining a copy > @@ -1213,17 +1215,28 @@ static void gt64120_realize(DeviceState *dev, Error **errp) > > static void gt64120_pci_realize(PCIDevice *d, Error **errp) > { > - /* FIXME: Malta specific hw assumptions ahead */ > + > + /* Values from chapter 17.16 "PCI Configuration" */ > + > pci_set_word(d->config + PCI_COMMAND, 0); > pci_set_word(d->config + PCI_STATUS, > PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); > pci_config_set_prog_interface(d->config, 0); > + > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff009); > + If you make these writeable, then you should set them on reset, as opposed to unrealize. > pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); > pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); > pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); > pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); > pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); > pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); > + > pci_set_byte(d->config + 0x3d, 0x01); > } > > -- > 2.45.2
diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index e02efc9e2e..0b00e98e0a 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1,6 +1,8 @@ /* * QEMU GT64120 PCI host * + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) + * * Copyright (c) 2006,2007 Aurelien Jarno * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -1213,17 +1215,28 @@ static void gt64120_realize(DeviceState *dev, Error **errp) static void gt64120_pci_realize(PCIDevice *d, Error **errp) { - /* FIXME: Malta specific hw assumptions ahead */ + + /* Values from chapter 17.16 "PCI Configuration" */ + pci_set_word(d->config + PCI_COMMAND, 0); pci_set_word(d->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff009); + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); + pci_set_byte(d->config + 0x3d, 0x01); }
When booting Linux we see: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) This is due to missing base address register write mask. Add it to get: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] Mention the datasheet referenced. Remove the "Malta assumptions ahead" comment since the reset values from the datasheet are used. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/pci-host/gt64120.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)