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envelope-from=atishp@rivosinc.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Counter delegation/configuration extension requires the following extensions to be enabled. 1. Smcdeleg - To enable counter delegation from M to S 2. S[m|s]csrind - To enable indirect access CSRs 3. Smstateen - Indirect CSR extensions depend on it. 4. Sscofpmf - To enable counter overflow feature 5. S[m|s]aia - To enable counter overflow feature in virtualization 6. Smcntrpmf - To enable privilege mode filtering for cycle/instret While first 3 are mandatory to enable the counter delegation, next 3 set of extension are preferred to enable all the PMU related features. That's why, enable all of these if Ssccfg extension is enabled from the commandline. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 22ba43c7ff2a..abebfcc46dea 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2665,8 +2665,20 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { NULL }; +static RISCVCPUPreferredExtsRule SSCCFG_PREFERRED = { + .ext = CPU_CFG_OFFSET(ext_ssccfg), + .preferred_multi_exts = { + CPU_CFG_OFFSET(ext_smcsrind), CPU_CFG_OFFSET(ext_sscsrind), + CPU_CFG_OFFSET(ext_ssaia), CPU_CFG_OFFSET(ext_smaia), + CPU_CFG_OFFSET(ext_smstateen), CPU_CFG_OFFSET(ext_sscofpmf), + CPU_CFG_OFFSET(ext_smcntrpmf), CPU_CFG_OFFSET(ext_smcdeleg), + + RISCV_PREFRRED_EXTS_RULE_END + }, +}; + RISCVCPUPreferredExtsRule *riscv_multi_ext_preferred_rules[] = { - NULL + &SSCCFG_PREFERRED, NULL }; static Property riscv_cpu_properties[] = {