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Mon, 22 Jul 2024 05:05:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHVepP+xxO5pGcHlPO+wKcXAjNJ4FPyvbSy3siSoBPH/qkVtasWjrzo0eqA/o1biA4AQ2t1vQ== X-Received: by 2002:a17:907:2d94:b0:a72:84c9:cedc with SMTP id a640c23a62f3a-a7a01115d81mr1346833166b.8.1721649952009; Mon, 22 Jul 2024 05:05:52 -0700 (PDT) Received: from avogadro.local ([151.95.101.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7a3c91e2e8sm415014066b.156.2024.07.22.05.05.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 05:05:51 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 4/7] hpet: place read-only bits directly in "new_val" Date: Mon, 22 Jul 2024 14:05:38 +0200 Message-ID: <20240722120541.70790-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240722120541.70790-1-pbonzini@redhat.com> References: <20240722120541.70790-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.133, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The variable "val" is used for two different purposes. As an intermediate value when writing configuration registers, and to store the cleared bits when writing ISR. Use "new_val" for the former, and rename the variable so that it is clearer for the latter case. Signed-off-by: Paolo Bonzini --- hw/timer/hpet.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 380e272fbeb..831e5a95b09 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -510,7 +510,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr, { int i; HPETState *s = opaque; - uint64_t old_val, new_val, val; + uint64_t old_val, new_val, cleared; trace_hpet_ram_write(addr, value); old_val = hpet_ram_read(opaque, addr, 4); @@ -536,13 +536,12 @@ static void hpet_ram_write(void *opaque, hwaddr addr, */ update_irq(timer, 0); } - val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); - timer->config = (timer->config & 0xffffffff00000000ULL) | val; + new_val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); + timer->config = (timer->config & 0xffffffff00000000ULL) | new_val; if (activating_bit(old_val, new_val, HPET_TN_ENABLE) && (s->isr & (1 << timer_id))) { update_irq(timer, 1); } - if (new_val & HPET_TN_32BIT) { timer->cmp = (uint32_t)timer->cmp; timer->period = (uint32_t)timer->period; @@ -623,8 +622,8 @@ static void hpet_ram_write(void *opaque, hwaddr addr, case HPET_ID: return; case HPET_CFG: - val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); - s->config = (s->config & 0xffffffff00000000ULL) | val; + new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); + s->config = (s->config & 0xffffffff00000000ULL) | new_val; if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { /* Enable main counter and interrupt generation. */ s->hpet_offset = @@ -658,9 +657,9 @@ static void hpet_ram_write(void *opaque, hwaddr addr, trace_hpet_invalid_hpet_cfg(4); break; case HPET_STATUS: - val = new_val & s->isr; + cleared = new_val & s->isr; for (i = 0; i < s->num_timers; i++) { - if (val & (1 << i)) { + if (cleared & (1 << i)) { update_irq(&s->timer[i], 0); } }