@@ -164,6 +164,7 @@ struct AspeedSoCClass {
const hwaddr *memmap;
uint32_t num_cpus;
qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
+ bool (*boot_from_emmc)(AspeedSoCState *s);
};
const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
@@ -646,6 +646,13 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
}
}
+static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s)
+{
+ uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu),
+ "hw-strap1", &error_abort);
+ return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC);
+}
+
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
{
static const char * const valid_cpu_types[] = {
@@ -673,6 +680,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
sc->memmap = aspeed_soc_ast2600_memmap;
sc->num_cpus = 2;
sc->get_irq = aspeed_soc_ast2600_get_irq;
+ sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc;
}
static const TypeInfo aspeed_soc_ast2600_types[] = {
@@ -134,6 +134,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
}
}
+static bool aspeed_soc_boot_from_emmc(AspeedSoCState *s)
+{
+ return false;
+}
+
static Property aspeed_soc_properties[] = {
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
@@ -145,9 +150,11 @@ static Property aspeed_soc_properties[] = {
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
dc->realize = aspeed_soc_realize;
device_class_set_props(dc, aspeed_soc_properties);
+ sc->boot_from_emmc = aspeed_soc_boot_from_emmc;
}
static const TypeInfo aspeed_soc_types[] = {