| Message ID | 20240716162617.32161-14-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | ppc/pnv: Better big-core model, lpar-per-core, PC unit | expand |
On 7/16/24 18:26, Nicholas Piggin wrote: > Power9 CPUs have a core thread state register accessible via SPRC/SPRD > indirect registers. This register includes a bit for big-core mode, > which skiboot requires. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > target/ppc/misc_helper.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c > index 692e48e6bc..e69236d2de 100644 > --- a/target/ppc/misc_helper.c > +++ b/target/ppc/misc_helper.c > @@ -319,6 +319,23 @@ target_ulong helper_load_sprd(CPUPPCState *env) > case 0: /* SCRATCH0-3 */ > case 1: /* SCRATCH4-7 */ > return pc->scratch[(sprc >> 3) & 0x7]; > + > + case 0x1e0: /* core thread state */ > + if (env->excp_model == POWERPC_EXCP_POWER9) { > + /* > + * Only implement for POWER9 because skiboot uses it to check > + * big-core mode. Other bits are unimplemented so we would > + * prefer to get unimplemented message on POWER10 if it were > + * used anywhere. > + */ > + if (pc->big_core) { > + return PPC_BIT(63); > + } else { > + return 0; > + } > + } > + /* fallthru */ > + > default: > qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" > TARGET_FMT_lx"\n", sprc);
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 692e48e6bc..e69236d2de 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -319,6 +319,23 @@ target_ulong helper_load_sprd(CPUPPCState *env) case 0: /* SCRATCH0-3 */ case 1: /* SCRATCH4-7 */ return pc->scratch[(sprc >> 3) & 0x7]; + + case 0x1e0: /* core thread state */ + if (env->excp_model == POWERPC_EXCP_POWER9) { + /* + * Only implement for POWER9 because skiboot uses it to check + * big-core mode. Other bits are unimplemented so we would + * prefer to get unimplemented message on POWER10 if it were + * used anywhere. + */ + if (pc->big_core) { + return PPC_BIT(63); + } else { + return 0; + } + } + /* fallthru */ + default: qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" TARGET_FMT_lx"\n", sprc);
Power9 CPUs have a core thread state register accessible via SPRC/SPRD indirect registers. This register includes a bit for big-core mode, which skiboot requires. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/misc_helper.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)