From patchwork Fri Jul 12 02:36:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changqi Lu X-Patchwork-Id: 1959663 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bytedance.com header.i=@bytedance.com header.a=rsa-sha256 header.s=google header.b=Jlm9kJ+m; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WKwmQ4JPlz1xqj for ; Fri, 12 Jul 2024 12:39:50 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sS6AQ-0004wy-QN; Thu, 11 Jul 2024 22:37:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sS6AN-0004eA-JP for qemu-devel@nongnu.org; Thu, 11 Jul 2024 22:37:47 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sS6AJ-0003RY-Vs for qemu-devel@nongnu.org; Thu, 11 Jul 2024 22:37:45 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-75c3afd7a50so1111323a12.2 for ; Thu, 11 Jul 2024 19:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1720751862; x=1721356662; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tjqh17JUE1WkBpchsBFPlHMHCUXRZeQxBDgeEciSrXM=; b=Jlm9kJ+mHoaueUIwD4D2hJQ7voTsHbLXo7tdiVh9OIEBuofwp1UUb4DgDt8hvjJgpj C/xqLdJSi/yLSCSQFAN6hww1nO+vbaYCTSb1cg/3FbJhe0gfGZy7FycC7lerjzNjTNqN R3KoEBdZ2bC7erKo5FKlIO0igIgeQx5gUq+zTv9rxe9kBQLLTeoOGasRFHNey6/ckg98 V1pI+YDamRSEHikNcMuJmwx/V51OqEk85VqjOOPE3vA+Nj2avFyFcxzU6hSySAbc9TqK 3C/U18eLw7vWUvNdPqCWOkhkUGk0j+kVLCMOaaWp7koFOa+HJzoWpRj5M2akK62QM8L1 NSpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720751862; x=1721356662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tjqh17JUE1WkBpchsBFPlHMHCUXRZeQxBDgeEciSrXM=; b=R075fBbq/0i3W/pvNf646+JmSBwfgfggzetrunBSj32+td1MYKREMcQs5SpZf8HLiQ 7ku9HfIyjeCZJ1kW8ep3uUgi5xu68i1iH+JJfzwehMSspEroXYl2ufhB2GKBCBQhK/30 E/Zh7NhS5JND8Q+9UTouY+ICRUJbixc9tSkBcrL4URwZyqRm5lCPECN3KFwB0+TdNBVd IR5tZJtO0lCQH8apFRhuZOO0En/To6ZuyjKDZge4vg/UxgAiRYfHs4MZQAHZd5a5hq7F 15+pZaOxVpD4S4ZgphGfU2CBnJViMa9vix0vdIqEsC9RXC6JxrkVK0GWjtaqtBTKOWzH tqQQ== X-Forwarded-Encrypted: i=1; AJvYcCVaguGB67LmwbembVI+ceiwIXFP4/t5xy6B0No3UsWdhgtNVghqxQqz8E/Kmhv8IsDo81xrbn8tc1QdO2jXEywYDshPJnY= X-Gm-Message-State: AOJu0Yx+pcw8q3n9Zk20H4DGEykrmgWYOoKM7P3h7mi1jx1aFxjy6r3Q MkVUFgTko1ltVUr2M43N0SKYYfZ9/Xv1OytSYBJ3QyTMFilYFQhkMOKl5XQUBf8= X-Google-Smtp-Source: AGHT+IEjVL9cZy3eRqqX9+54rtDPWqDggxRVctbZoAALnTWfcVZQ4MmTJZB5FkKX1H0+uUIDpA2B6g== X-Received: by 2002:a05:6a20:8404:b0:1bc:e978:8bf2 with SMTP id adf61e73a8af0-1c29821fb4fmr10642717637.23.1720751862540; Thu, 11 Jul 2024 19:37:42 -0700 (PDT) Received: from TF4D9JK212.bytedance.net ([61.213.176.12]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cacd65fc43sm297453a91.39.2024.07.11.19.37.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 11 Jul 2024 19:37:42 -0700 (PDT) From: Changqi Lu To: qemu-block@nongnu.org, qemu-devel@nongnu.org Cc: kwolf@redhat.com, hreitz@redhat.com, stefanha@redhat.com, fam@euphon.net, ronniesahlberg@gmail.com, pbonzini@redhat.com, pl@dlhnet.de, kbusch@kernel.org, its@irrelevant.dk, foss@defmacro.it, philmd@linaro.org, pizhenwei@bytedance.com, Changqi Lu , Klaus Jensen Subject: [PATCH v9 07/10] hw/nvme: add helper functions for converting reservation types Date: Fri, 12 Jul 2024 10:36:47 +0800 Message-Id: <20240712023650.45626-8-luchangqi.123@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20240712023650.45626-1-luchangqi.123@bytedance.com> References: <20240712023650.45626-1-luchangqi.123@bytedance.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=luchangqi.123@bytedance.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This commit introduces two helper functions that facilitate the conversion between the reservation types used in the NVME protocol and those used in the block layer. Reviewed-by: Klaus Jensen Reviewed-by: Stefan Hajnoczi Signed-off-by: Changqi Lu Signed-off-by: zhenwei pi --- hw/nvme/nvme.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index bed8191bd5..6d0e456348 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -474,6 +474,90 @@ static inline const char *nvme_io_opc_str(uint8_t opc) } } +static inline NvmeResvType block_pr_type_to_nvme(BlockPrType type) +{ + switch (type) { + case BLK_PR_WRITE_EXCLUSIVE: + return NVME_RESV_WRITE_EXCLUSIVE; + case BLK_PR_EXCLUSIVE_ACCESS: + return NVME_RESV_EXCLUSIVE_ACCESS; + case BLK_PR_WRITE_EXCLUSIVE_REGS_ONLY: + return NVME_RESV_WRITE_EXCLUSIVE_REGS_ONLY; + case BLK_PR_EXCLUSIVE_ACCESS_REGS_ONLY: + return NVME_RESV_EXCLUSIVE_ACCESS_REGS_ONLY; + case BLK_PR_WRITE_EXCLUSIVE_ALL_REGS: + return NVME_RESV_WRITE_EXCLUSIVE_ALL_REGS; + case BLK_PR_EXCLUSIVE_ACCESS_ALL_REGS: + return NVME_RESV_EXCLUSIVE_ACCESS_ALL_REGS; + } + + return 0; +} + +static inline BlockPrType nvme_pr_type_to_block(NvmeResvType type) +{ + switch (type) { + case NVME_RESV_WRITE_EXCLUSIVE: + return BLK_PR_WRITE_EXCLUSIVE; + case NVME_RESV_EXCLUSIVE_ACCESS: + return BLK_PR_EXCLUSIVE_ACCESS; + case NVME_RESV_WRITE_EXCLUSIVE_REGS_ONLY: + return BLK_PR_WRITE_EXCLUSIVE_REGS_ONLY; + case NVME_RESV_EXCLUSIVE_ACCESS_REGS_ONLY: + return BLK_PR_EXCLUSIVE_ACCESS_REGS_ONLY; + case NVME_RESV_WRITE_EXCLUSIVE_ALL_REGS: + return BLK_PR_WRITE_EXCLUSIVE_ALL_REGS; + case NVME_RESV_EXCLUSIVE_ACCESS_ALL_REGS: + return BLK_PR_EXCLUSIVE_ACCESS_ALL_REGS; + } + + return 0; +} + +static inline uint8_t nvme_pr_cap_to_block(uint16_t nvme_pr_cap) +{ + uint8_t res = 0; + + res |= (nvme_pr_cap & NVME_PR_CAP_PTPL) ? + NVME_PR_CAP_PTPL : 0; + res |= (nvme_pr_cap & NVME_PR_CAP_WR_EX) ? + BLK_PR_CAP_WR_EX : 0; + res |= (nvme_pr_cap & NVME_PR_CAP_EX_AC) ? + BLK_PR_CAP_EX_AC : 0; + res |= (nvme_pr_cap & NVME_PR_CAP_WR_EX_RO) ? + BLK_PR_CAP_WR_EX_RO : 0; + res |= (nvme_pr_cap & NVME_PR_CAP_EX_AC_RO) ? + BLK_PR_CAP_EX_AC_RO : 0; + res |= (nvme_pr_cap & NVME_PR_CAP_WR_EX_AR) ? + BLK_PR_CAP_WR_EX_AR : 0; + res |= (nvme_pr_cap & NVME_PR_CAP_EX_AC_AR) ? + BLK_PR_CAP_EX_AC_AR : 0; + + return res; +} + +static inline uint8_t block_pr_cap_to_nvme(uint8_t block_pr_cap) +{ + uint16_t res = 0; + + res |= (block_pr_cap & BLK_PR_CAP_PTPL) ? + NVME_PR_CAP_PTPL : 0; + res |= (block_pr_cap & BLK_PR_CAP_WR_EX) ? + NVME_PR_CAP_WR_EX : 0; + res |= (block_pr_cap & BLK_PR_CAP_EX_AC) ? + NVME_PR_CAP_EX_AC : 0; + res |= (block_pr_cap & BLK_PR_CAP_WR_EX_RO) ? + NVME_PR_CAP_WR_EX_RO : 0; + res |= (block_pr_cap & BLK_PR_CAP_EX_AC_RO) ? + NVME_PR_CAP_EX_AC_RO : 0; + res |= (block_pr_cap & BLK_PR_CAP_WR_EX_AR) ? + NVME_PR_CAP_WR_EX_AR : 0; + res |= (block_pr_cap & BLK_PR_CAP_EX_AC_AR) ? + NVME_PR_CAP_EX_AC_AR : 0; + + return res; +} + typedef struct NvmeSQueue { struct NvmeCtrl *ctrl; uint16_t sqid;