diff mbox series

[PULL,17/40] tests/tcg/arm: Use -march and -mfpu for fcvt

Message ID	20240705153052.1219696-18-alex.bennee@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org> To: qemu-devel@nongnu.org Cc: Richard Henderson <richard.henderson@linaro.org>, Akihiko Odaki <akihiko.odaki@daynix.com>, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 17/40] tests/tcg/arm: Use -march and -mfpu for fcvt Date: Fri, 5 Jul 2024 16:30:29 +0100 Message-Id: <20240705153052.1219696-18-alex.bennee@linaro.org> In-Reply-To: <20240705153052.1219696-1-alex.bennee@linaro.org> References: <20240705153052.1219696-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/40] tests/lcitool: fix debian-i686-cross toolchain prefix \| expand [PULL,01/40] tests/lcitool: fix debian-i686-cross toolchain prefix [PULL,02/40] testing: restore some testing for i686 [PULL,03/40] tracepoints: move physmem trace points [PULL,04/40] hw/core: ensure kernel_end never gets used undefined [PULL,05/40] tests/docker: Specify --userns keep-id for Podman [PULL,06/40] tests/tcg/minilib: Constify digits in print_num [PULL,07/40] tests/tcg: Adjust variable defintion from cc-option [PULL,08/40] tests/tcg/aarch64: Drop -fno-tree-loop-distribute-patterns [PULL,09/40] tests/tcg/aarch64: Explicitly specify register width [PULL,10/40] tests/tcg/aarch64: Fix irg operand type [PULL,11/40] tests/tcg/aarch64: Do not use x constraint [PULL,12/40] tests/tcg/aarch64: Add -fno-integrated-as for sme [PULL,13/40] tests/tcg/arm: Fix fcvt result messages [PULL,14/40] tests/tcg/arm: Drop -N from LDFLAGS [PULL,15/40] tests/tcg/arm: Use -fno-integrated-as for test-arm-iwmmxt [PULL,16/40] tests/tcg/arm: Manually register allocate half-precision numbers [PULL,17/40] tests/tcg/arm: Use -march and -mfpu for fcvt [PULL,18/40] tests/tcg/arm: Use vmrs/vmsr instead of mcr/mrc [PULL,19/40] linux-user/main: Suppress out-of-range comparison warning for clang [PULL,20/40] gitlab: don't bother with KVM for TCI builds [PULL,21/40] test/plugin: make insn plugin less noisy by default [PULL,22/40] test/plugins: preserve the instruction record over translations [PULL,23/40] plugins/lockstep: preserve sock_path [PULL,24/40] plugins/lockstep: make mixed-mode safe [PULL,25/40] plugins/lockstep: mention the one-insn-per-tb option [PULL,26/40] plugins/lockstep: clean-up output [PULL,27/40] plugins: Ensure vCPU index is assigned in init/exit hooks [PULL,28/40] plugins: Free CPUPluginState before destroying vCPU state [PULL,29/40] accel/tcg: Move qemu_plugin_vcpu_init__async() to plugins/ [PULL,30/40] gdbstub: Clean up process_string_cmd [PULL,31/40] gdbstub: Move GdbCmdParseEntry into a new header file [PULL,32/40] gdbstub: Add support for target-specific stubs [PULL,33/40] target/arm: Fix exception case in allocation_tag_mem_probe [PULL,34/40] target/arm: Make some MTE helpers widely available [PULL,35/40] target/arm: Factor out code for setting MTE TCF0 field [PULL,36/40] gdbstub: Make hex conversion function non-internal [PULL,37/40] gdbstub: Pass CPU context to command handler [PULL,38/40] gdbstub: Use true to set cmd_startswith [PULL,39/40] gdbstub: Add support for MTE in user mode [PULL,40/40] tests/tcg/aarch64: Add MTE gdbstub tests

Commit Message

Alex Bennée July 5, 2024, 3:30 p.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>

Clang requires the architecture to be set properly
in order to assemble the half-precision instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240630190050.160642-13-richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240705084047.857176-18-alex.bennee@linaro.org>

diff mbox series

Patch

diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
index 95f891bf8c..8e287191af 100644
--- a/tests/tcg/arm/Makefile.target
+++ b/tests/tcg/arm/Makefile.target
@@ -29,8 +29,8 @@  test-arm-iwmmxt: test-arm-iwmmxt.S
 
 # Float-convert Tests
 ARM_TESTS += fcvt
-fcvt: LDFLAGS+=-lm
-# fcvt: CFLAGS+=-march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
+fcvt: LDFLAGS += -lm
+fcvt: CFLAGS += -march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
 run-fcvt: fcvt
 	$(call run-test,fcvt,$(QEMU) $<)
 	$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)