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([2804:7f0:b400:8dcb:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4a75ed69csm10641863a91.14.2024.06.16.23.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jun 2024 23:29:25 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, philmd@linaro.org, peter.maydell@linaro.org, alex.bennee@linaro.org, richard.henderson@linaro.org Cc: gustavo.romero@linaro.org Subject: [PATCH v3 6/9] target/arm: Factor out code for setting MTE TCF0 field Date: Mon, 17 Jun 2024 06:28:46 +0000 Message-Id: <20240617062849.3531745-7-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240617062849.3531745-1-gustavo.romero@linaro.org> References: <20240617062849.3531745-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set across the board. Signed-off-by: Gustavo Romero --- linux-user/aarch64/target_prctl.h | 22 ++--------------- target/arm/tcg/mte_user_helper.h | 40 +++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 20 deletions(-) create mode 100644 target/arm/tcg/mte_user_helper.h diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index aa8e203c15..cfc8567eac 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -7,6 +7,7 @@ #define AARCH64_TARGET_PRCTL_H #include "target/arm/cpu-features.h" +#include "target/arm/tcg/mte_user_helper.h" static abi_long do_prctl_sve_get_vl(CPUArchState *env) { @@ -173,26 +174,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2) env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE; if (cpu_isar_feature(aa64_mte, cpu)) { - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * - * The kernel has a per-cpu configuration for the sysadmin, - * /sys/devices/system/cpu/cpu/mte_tcf_preferred, - * which qemu does not implement. - * - * Because there is no performance difference between the modes, and - * because SYNC is most useful for debugging MTE errors, choose SYNC - * as the preferred mode. With this preference, and the way the API - * uses only two bits, there is no way for the program to select - * ASYMM mode. - */ - unsigned tcf = 0; - if (arg2 & PR_MTE_TCF_SYNC) { - tcf = 1; - } else if (arg2 & PR_MTE_TCF_ASYNC) { - tcf = 2; - } - env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); + arm_set_mte_tcf0(env, arg2); /* * Write PR_MTE_TAG to GCR_EL1[Exclude]. diff --git a/target/arm/tcg/mte_user_helper.h b/target/arm/tcg/mte_user_helper.h new file mode 100644 index 0000000000..dee74d0923 --- /dev/null +++ b/target/arm/tcg/mte_user_helper.h @@ -0,0 +1,40 @@ +/* + * ARM MemTag convenience functions. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef MTE_H +#define MTE_H + +#ifdef CONFIG_USER_ONLY +#include "sys/prctl.h" + +static inline void arm_set_mte_tcf0(CPUArchState *env, abi_long value) +{ + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * + * The kernel has a per-cpu configuration for the sysadmin, + * /sys/devices/system/cpu/cpu/mte_tcf_preferred, + * which qemu does not implement. + * + * Because there is no performance difference between the modes, and + * because SYNC is most useful for debugging MTE errors, choose SYNC + * as the preferred mode. With this preference, and the way the API + * uses only two bits, there is no way for the program to select + * ASYMM mode. + */ + unsigned tcf = 0; + if (value & PR_MTE_TCF_SYNC) { + tcf = 1; + } else if (value & PR_MTE_TCF_ASYNC) { + tcf = 2; + } + env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); +} +#endif /* CONFIG_USER_ONLY */ + +#endif /* MTE_H */