| Message ID | 20240614093026.328271-4-sai.pavan.boddu@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add DCC uart console support | expand |
On Fri, 14 Jun 2024 at 10:30, Sai Pavan Boddu <sai.pavan.boddu@amd.com> wrote: > > MDCCSR_EL0 is aarch64 varient of DBGDSCRint, so utilize the same cpreg > offset. > > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> > --- > target/arm/debug_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c > index 7d856acddf..5deafa4d1f 100644 > --- a/target/arm/debug_helper.c > +++ b/target/arm/debug_helper.c > @@ -970,7 +970,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, > .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, > .access = PL0_R, .accessfn = access_tdcc, > - .type = ARM_CP_CONST, .resetvalue = 0 }, > + .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1)}, /* Xilinx */ MDCCSR_EL0 and MDSCR_EL1 aren't the same thing -- MDCCSR_EL0 only has bits 30 and 29 (RXfull and TXfull), not the full contents of MDSCR_EL1. thanks -- PMM
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 7d856acddf..5deafa4d1f 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -970,7 +970,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, .access = PL0_R, .accessfn = access_tdcc, - .type = ARM_CP_CONST, .resetvalue = 0 }, + .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1)}, /* Xilinx */ /* * These registers belong to the Debug Communications Channel, * which is not implemented. However we implement RAZ/WI behaviour
MDCCSR_EL0 is aarch64 varient of DBGDSCRint, so utilize the same cpreg offset. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)