@@ -9,6 +9,7 @@
/* Digested version of <cpuid.h> */
#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */
+#define CPUINFO_CMOV (1u << 1)
#define CPUINFO_MOVBE (1u << 2)
#define CPUINFO_LZCNT (1u << 3)
#define CPUINFO_POPCNT (1u << 4)
@@ -157,6 +157,12 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define SOFTMMU_RESERVE_REGS \
(tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0)
+/* For 64-bit, we always know that CMOV is available. */
+#if TCG_TARGET_REG_BITS == 64
+# define have_cmov true
+#else
+# define have_cmov (cpuinfo & CPUINFO_CMOV)
+#endif
#define have_bmi2 (cpuinfo & CPUINFO_BMI2)
#define have_lzcnt (cpuinfo & CPUINFO_LZCNT)
@@ -1809,7 +1815,14 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
static void tcg_out_cmov(TCGContext *s, int jcc, int rexw,
TCGReg dest, TCGReg v1)
{
- tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1);
+ if (have_cmov) {
+ tcg_out_modrm(s, OPC_CMOVCC | jcc | rexw, dest, v1);
+ } else {
+ TCGLabel *over = gen_new_label();
+ tcg_out_jxx(s, jcc ^ 1, over, 1);
+ tcg_out_mov(s, TCG_TYPE_I32, dest, v1);
+ tcg_out_label(s, over);
+ }
}
static void tcg_out_movcond(TCGContext *s, int rexw, TCGCond cond,
@@ -34,6 +34,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
if (max >= 1) {
__cpuid(1, a, b, c, d);
+ info |= (d & bit_CMOV ? CPUINFO_CMOV : 0);
info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0);
info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0);
info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
This reverts commit e68e97ce55b3d17af22dd62c3b3dc72f761b0862. Revert in preparation to rolling back x86_64-v2 ISA requirement. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> --- host/include/i386/host/cpuinfo.h | 1 + tcg/i386/tcg-target.c.inc | 15 ++++++++++++++- util/cpuinfo-i386.c | 1 + 3 files changed, 16 insertions(+), 1 deletion(-)