| Message ID | 20240606121657.254308-3-adityag@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | Power11 support for QEMU [PSeries] | expand |
On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote: > Add CPU target code to add support for new Power11 Processor. > > Power11 core is same as Power10, hence reuse functions defined for > Power10. > > Cc: Cédric Le Goater <clg@kaod.org> > Cc: Daniel Henrique Barboza <danielhb413@gmail.com> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com> > Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com> > Cc: Nicholas Piggin <npiggin@gmail.com> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> > --- > target/ppc/compat.c | 7 ++++++ > target/ppc/cpu-models.c | 3 +++ > target/ppc/cpu-models.h | 3 +++ > target/ppc/cpu_init.c | 54 +++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 67 insertions(+) > > diff --git a/target/ppc/compat.c b/target/ppc/compat.c > index ebef2cccecf3..12dd8ae290ca 100644 > --- a/target/ppc/compat.c > +++ b/target/ppc/compat.c > @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = { > .pcr_level = PCR_COMPAT_3_10, > .max_vthreads = 8, > }, > + { /* POWER11, ISA3.10 */ > + .name = "power11", > + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, Might call that _P11 rather than _PLUS, but I can fold that in my tree. > + .pcr = PCR_COMPAT_3_10, > + .pcr_level = PCR_COMPAT_3_10, > + .max_vthreads = 8, > + }, > }; > > static const CompatInfo *compat_by_pvr(uint32_t pvr) > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > index f2301b43f78b..ece348178188 100644 > --- a/target/ppc/cpu-models.c > +++ b/target/ppc/cpu-models.c > @@ -734,6 +734,8 @@ > "POWER9 v2.2") > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > "POWER10 v2.0") > + POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER11, > + "POWER11_v2.0") > #endif /* defined (TARGET_PPC64) */ > > /***************************************************************************/ > @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { > { "power8nvl", "power8nvl_v1.0" }, > { "power9", "power9_v2.2" }, > { "power10", "power10_v2.0" }, > + { "power11", "power11_v2.0" }, > #endif > > /* Generic PowerPCs */ > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index 0229ef3a9a5c..ef74e387b047 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -354,6 +354,8 @@ enum { > CPU_POWERPC_POWER10_BASE = 0x00800000, > CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > + CPU_POWERPC_POWER11_BASE = 0x00820000, > + CPU_POWERPC_POWER11_DD20 = 0x00821200, > CPU_POWERPC_970_v22 = 0x00390202, > CPU_POWERPC_970FX_v10 = 0x00391100, > CPU_POWERPC_970FX_v20 = 0x003C0200, > @@ -391,6 +393,7 @@ enum { > CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, > CPU_POWERPC_LOGICAL_3_00 = 0x0F000005, > CPU_POWERPC_LOGICAL_3_10 = 0x0F000006, > + CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007, > }; > > /* System version register (used on MPC 8xxx) */ > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 3d8a112935ae..9aa098935d05 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6669,6 +6669,60 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) > pcc->l1_icache_size = 0x8000; > } > > +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > +{ > + uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; > + uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; > + > + if (!best && (base == CPU_POWERPC_POWER11_BASE)) { > + return true; > + } > + > + if (base != pcc_base) { > + return false; > + } > + > + if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { > + return true; > + } > + > + return false; > +} > + > +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); > + > + dc->fw_name = "PowerPC,POWER11"; > + dc->desc = "POWER11"; > + pcc->pvr_match = ppc_pvr_match_power11; > + pcc->pcr_mask = POWERPC_POWER10_PCC_PCR_MASK; > + pcc->pcr_supported = POWERPC_POWER10_PCC_PCR_SUPPORTED; > + pcc->init_proc = init_proc_POWER10; > + pcc->check_pow = check_pow_nocheck; > + pcc->check_attn = check_attn_hid0_power9; > + pcc->insns_flags = POWERPC_FAMILY_POWER9_INSNS_FLAGS; /* same as P9 */ > + pcc->insns_flags2 = POWERPC_FAMILY_POWER10_INSNS_FLAGS2; > + pcc->msr_mask = POWERPC_POWER10_PCC_MSR_MASK; > + pcc->lpcr_mask = POWERPC_POWER10_PCC_LPCR_MASK; BTW., I still think all these new macros should be named after the exact CPU, e.g., all these should be called POWER11 and the differences or sameness should be handled in cpu_init.h. I might tweak that and the names a bit locally (e.g., why is one type of define called POWERPC_FAMILY_x and another called POWERPC_x_PCC), but that's not a big deal and mostly an exercise in bike shed painting. The functionality of the patch looks okay. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> > + > + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; > + pcc->mmu_model = POWERPC_MMU_3_00; > +#if !defined(CONFIG_USER_ONLY) > + /* segment page size remain the same */ > + pcc->hash64_opts = &ppc_hash64_opts_POWER7; > + pcc->radix_page_info = &POWER10_radix_page_info; > + pcc->lrg_decr_bits = 56; > +#endif > + pcc->excp_model = POWERPC_EXCP_POWER10; > + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; > + pcc->bfd_mach = bfd_mach_ppc64; > + pcc->flags = POWERPC_POWER10_PCC_FLAGS; > + pcc->l1_dcache_size = 0x8000; > + pcc->l1_icache_size = 0x8000; > +} > + > #if !defined(CONFIG_USER_ONLY) > void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) > {
Hi Nick, On 23/07/24 10:00, Nicholas Piggin wrote: >> <...snip...> >> >> + { /* POWER11, ISA3.10 */ >> + .name = "power11", >> + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, > Might call that _P11 rather than _PLUS, but I can fold that in my tree. Sure, makes sense, I can make these changes, and send a v2 soon. >> <...snip...> >> >> + >> +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) >> +{ >> + DeviceClass *dc = DEVICE_CLASS(oc); >> + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); >> + >> + dc->fw_name = "PowerPC,POWER11"; >> + dc->desc = "POWER11"; >> + pcc->pvr_match = ppc_pvr_match_power11; >> + pcc->pcr_mask = POWERPC_POWER10_PCC_PCR_MASK; >> + pcc->pcr_supported = POWERPC_POWER10_PCC_PCR_SUPPORTED; >> + pcc->init_proc = init_proc_POWER10; >> + pcc->check_pow = check_pow_nocheck; >> + pcc->check_attn = check_attn_hid0_power9; >> + pcc->insns_flags = POWERPC_FAMILY_POWER9_INSNS_FLAGS; /* same as P9 */ >> + pcc->insns_flags2 = POWERPC_FAMILY_POWER10_INSNS_FLAGS2; >> + pcc->msr_mask = POWERPC_POWER10_PCC_MSR_MASK; >> + pcc->lpcr_mask = POWERPC_POWER10_PCC_LPCR_MASK; > BTW., I still think all these new macros should be named after the exact > CPU, e.g., all these should be called POWER11 and the differences or > sameness should be handled in cpu_init.h. Got it, can create macros for the Power11 things also. Regarding this: > + pcc->check_attn = check_attn_hid0_power9; > + pcc->insns_flags = POWERPC_FAMILY_POWER9_INSNS_FLAGS; /* same as P9 */ Should I keep them same, or have *_POWER11_* counterparts ? > > I might tweak that and the names a bit locally (e.g., why is one type of > define called POWERPC_FAMILY_x and another called POWERPC_x_PCC), but > that's not a big deal and mostly an exercise in bike shed painting. The > functionality of the patch looks okay. I am okay if you want to do it, or i can do it in a separate follow up patch. > Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Thanks for the tag Nick ! - Aditya Gupta > >> + >> + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; >> + pcc->mmu_model = POWERPC_MMU_3_00; >> +#if !defined(CONFIG_USER_ONLY) >> + /* segment page size remain the same */ >> + pcc->hash64_opts = &ppc_hash64_opts_POWER7; >> + pcc->radix_page_info = &POWER10_radix_page_info; >> + pcc->lrg_decr_bits = 56; >> +#endif >> + pcc->excp_model = POWERPC_EXCP_POWER10; >> + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; >> + pcc->bfd_mach = bfd_mach_ppc64; >> + pcc->flags = POWERPC_POWER10_PCC_FLAGS; >> + pcc->l1_dcache_size = 0x8000; >> + pcc->l1_icache_size = 0x8000; >> +} >> + >> #if !defined(CONFIG_USER_ONLY) >> void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) >> {
On Thu Jun 6, 2024 at 10:16 PM AEST, Aditya Gupta wrote: > Add CPU target code to add support for new Power11 Processor. > > Power11 core is same as Power10, hence reuse functions defined for > Power10. > > Cc: Cédric Le Goater <clg@kaod.org> > Cc: Daniel Henrique Barboza <danielhb413@gmail.com> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com> > Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com> > Cc: Nicholas Piggin <npiggin@gmail.com> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> > --- > target/ppc/compat.c | 7 ++++++ > target/ppc/cpu-models.c | 3 +++ > target/ppc/cpu-models.h | 3 +++ > target/ppc/cpu_init.c | 54 +++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 67 insertions(+) > > diff --git a/target/ppc/compat.c b/target/ppc/compat.c > index ebef2cccecf3..12dd8ae290ca 100644 > --- a/target/ppc/compat.c > +++ b/target/ppc/compat.c > @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = { > .pcr_level = PCR_COMPAT_3_10, > .max_vthreads = 8, > }, > + { /* POWER11, ISA3.10 */ > + .name = "power11", > + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, > + .pcr = PCR_COMPAT_3_10, > + .pcr_level = PCR_COMPAT_3_10, > + .max_vthreads = 8, > + }, > }; > > static const CompatInfo *compat_by_pvr(uint32_t pvr) > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > index f2301b43f78b..ece348178188 100644 > --- a/target/ppc/cpu-models.c > +++ b/target/ppc/cpu-models.c > @@ -734,6 +734,8 @@ > "POWER9 v2.2") > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > "POWER10 v2.0") > + POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER11, > + "POWER11_v2.0") > #endif /* defined (TARGET_PPC64) */ > > /***************************************************************************/ > @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { > { "power8nvl", "power8nvl_v1.0" }, > { "power9", "power9_v2.2" }, > { "power10", "power10_v2.0" }, > + { "power11", "power11_v2.0" }, > #endif > > /* Generic PowerPCs */ > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index 0229ef3a9a5c..ef74e387b047 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -354,6 +354,8 @@ enum { > CPU_POWERPC_POWER10_BASE = 0x00800000, > CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > + CPU_POWERPC_POWER11_BASE = 0x00820000, > + CPU_POWERPC_POWER11_DD20 = 0x00821200, > CPU_POWERPC_970_v22 = 0x00390202, > CPU_POWERPC_970FX_v10 = 0x00391100, > CPU_POWERPC_970FX_v20 = 0x003C0200, > @@ -391,6 +393,7 @@ enum { > CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, > CPU_POWERPC_LOGICAL_3_00 = 0x0F000005, > CPU_POWERPC_LOGICAL_3_10 = 0x0F000006, > + CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007, _PLUS (or POWER7P etc) was a model name itself and had different PVR and maybe different features in some cases, which is a bit different to the situation here. Could be confusing to call this _PLUS, so I would just call it _3_10_P11, as annoying as it is. Thanks, Nick
diff --git a/target/ppc/compat.c b/target/ppc/compat.c index ebef2cccecf3..12dd8ae290ca 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = { .pcr_level = PCR_COMPAT_3_10, .max_vthreads = 8, }, + { /* POWER11, ISA3.10 */ + .name = "power11", + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, + .pcr = PCR_COMPAT_3_10, + .pcr_level = PCR_COMPAT_3_10, + .max_vthreads = 8, + }, }; static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index f2301b43f78b..ece348178188 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -734,6 +734,8 @@ "POWER9 v2.2") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, "POWER10 v2.0") + POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER11, + "POWER11_v2.0") #endif /* defined (TARGET_PPC64) */ /***************************************************************************/ @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { { "power8nvl", "power8nvl_v1.0" }, { "power9", "power9_v2.2" }, { "power10", "power10_v2.0" }, + { "power11", "power11_v2.0" }, #endif /* Generic PowerPCs */ diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a5c..ef74e387b047 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -354,6 +354,8 @@ enum { CPU_POWERPC_POWER10_BASE = 0x00800000, CPU_POWERPC_POWER10_DD1 = 0x00801100, CPU_POWERPC_POWER10_DD20 = 0x00801200, + CPU_POWERPC_POWER11_BASE = 0x00820000, + CPU_POWERPC_POWER11_DD20 = 0x00821200, CPU_POWERPC_970_v22 = 0x00390202, CPU_POWERPC_970FX_v10 = 0x00391100, CPU_POWERPC_970FX_v20 = 0x003C0200, @@ -391,6 +393,7 @@ enum { CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, CPU_POWERPC_LOGICAL_3_00 = 0x0F000005, CPU_POWERPC_LOGICAL_3_10 = 0x0F000006, + CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007, }; /* System version register (used on MPC 8xxx) */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3d8a112935ae..9aa098935d05 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6669,6 +6669,60 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_icache_size = 0x8000; } +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) +{ + uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; + uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; + + if (!best && (base == CPU_POWERPC_POWER11_BASE)) { + return true; + } + + if (base != pcc_base) { + return false; + } + + if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { + return true; + } + + return false; +} + +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER11"; + dc->desc = "POWER11"; + pcc->pvr_match = ppc_pvr_match_power11; + pcc->pcr_mask = POWERPC_POWER10_PCC_PCR_MASK; + pcc->pcr_supported = POWERPC_POWER10_PCC_PCR_SUPPORTED; + pcc->init_proc = init_proc_POWER10; + pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_hid0_power9; + pcc->insns_flags = POWERPC_FAMILY_POWER9_INSNS_FLAGS; /* same as P9 */ + pcc->insns_flags2 = POWERPC_FAMILY_POWER10_INSNS_FLAGS2; + pcc->msr_mask = POWERPC_POWER10_PCC_MSR_MASK; + pcc->lpcr_mask = POWERPC_POWER10_PCC_LPCR_MASK; + + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; + pcc->mmu_model = POWERPC_MMU_3_00; +#if !defined(CONFIG_USER_ONLY) + /* segment page size remain the same */ + pcc->hash64_opts = &ppc_hash64_opts_POWER7; + pcc->radix_page_info = &POWER10_radix_page_info; + pcc->lrg_decr_bits = 56; +#endif + pcc->excp_model = POWERPC_EXCP_POWER10; + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_POWER10_PCC_FLAGS; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) {
Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Cc: Cédric Le Goater <clg@kaod.org> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: Frédéric Barrat <fbarrat@linux.ibm.com> Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> --- target/ppc/compat.c | 7 ++++++ target/ppc/cpu-models.c | 3 +++ target/ppc/cpu-models.h | 3 +++ target/ppc/cpu_init.c | 54 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 67 insertions(+)