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Tsirkin" , Marcel Apfelbaum , qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Nam Cao Subject: [PATCH v2] pci-bridge/xio3130_downstream: fix invalid link speed and link width Date: Wed, 29 May 2024 22:17:44 +0200 Message-Id: <20240529201744.15420-1-namcao@linutronix.de> MIME-Version: 1.0 Received-SPF: pass client-ip=2a0a:51c0:0:12e:550::1; envelope-from=namcao@linutronix.de; helo=galois.linutronix.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set link width to x1 and link speed to 2.5 Gb/s as specified by the datasheet. Without this, these fields in the link status register read zero, which is incorrect. This problem appeared since 3d67447fe7c2 ("pcie: Fill PCIESlot link fields to support higher speeds and widths"), which allows PCIe slot to set link width and link speed. However, if PCIe slot does not explicitly set these properties, they will be zero. Before this commit, the width and speed default to x1 and 2.5 Gb/s. Fixes: 3d67447fe7c2 ("pcie: Fill PCIESlot link fields to support higher speeds and widths") Signed-off-by: Nam Cao --- v2: implement this in .realize() instead --- hw/pci-bridge/xio3130_downstream.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 38a2361fa2..2df1ee203d 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -72,6 +72,9 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) pci_bridge_initfn(d, TYPE_PCIE_BUS); pcie_port_init_reg(d); + s->speed = QEMU_PCI_EXP_LNK_2_5GT; + s->width = QEMU_PCI_EXP_LNK_X1; + rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,