[RFC,03/10] target/ppc: Improve SPR indirect registers

SPRC/SPRD were recently added to all BookS CPUs supported, but
they are only tested on POWER9 and POWER10, so restrict them to
those CPUs.

SPR indirect scratch registers presently replicated per-CPU like
SMT SPRs, but the PnvCore is a better place for them since they
are restricted to P9/P10.

Also add SPR indirect read access to core thread state for POWER9
since skiboot accesses that when booting to check for big-core
mode.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 include/hw/ppc/pnv_core.h |  1 +
 target/ppc/cpu.h          |  3 --
 target/ppc/cpu_init.c     | 21 ++++++------
 target/ppc/misc_helper.c  | 67 ++++++++++++++++++++-------------------
 4 files changed, 46 insertions(+), 46 deletions(-)

Hi Nick,

On 5/26/24 17:56, Nicholas Piggin wrote:
> SPRC/SPRD were recently added to all BookS CPUs supported, but
> they are only tested on POWER9 and POWER10, so restrict them to
> those CPUs.
> 

Hope you mean to restrict to P9/10 for both spapr and pnv or just pnv ?

> SPR indirect scratch registers presently replicated per-CPU like
> SMT SPRs, but the PnvCore is a better place for them since they
> are restricted to P9/P10.
> 
> Also add SPR indirect read access to core thread state for POWER9
> since skiboot accesses that when booting to check for big-core
> mode.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>   include/hw/ppc/pnv_core.h |  1 +
>   target/ppc/cpu.h          |  3 --
>   target/ppc/cpu_init.c     | 21 ++++++------
>   target/ppc/misc_helper.c  | 67 ++++++++++++++++++++-------------------
>   4 files changed, 46 insertions(+), 46 deletions(-)
> 
> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
> index f434c71547..21297262c1 100644
> --- a/include/hw/ppc/pnv_core.h
> +++ b/include/hw/ppc/pnv_core.h
> @@ -53,6 +53,7 @@ struct PnvCore {
>       uint32_t hwid;
>       uint64_t hrmor;
>   
> +    target_ulong scratch[8]; /* SCRATCH registers */
>       struct pnv_tod_tbst pnv_tod_tbst;
>   
>       PnvChip *chip;
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 1e86658da6..dac13d4dac 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1253,9 +1253,6 @@ struct CPUArchState {
>       ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
>       struct CPUBreakpoint *ciabr_breakpoint;
>       struct CPUWatchpoint *dawr0_watchpoint;
> -
> -    /* POWER CPU regs/state */
> -    target_ulong scratch[8]; /* SCRATCH registers (shared across core) */
>   #endif
>       target_ulong sr[32];   /* segment registers */
>       uint32_t nb_BATs;      /* number of BATs */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 01e358a4a5..ae483e20c4 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -5759,16 +5759,6 @@ static void register_power_common_book4_sprs(CPUPPCState *env)
>                    SPR_NOACCESS, SPR_NOACCESS,
>                    &spr_read_generic, &spr_core_write_generic,
>                    0x00000000);
> -    spr_register_hv(env, SPR_POWER_SPRC, "SPRC",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_sprc,
> -                 0x00000000);
> -    spr_register_hv(env, SPR_POWER_SPRD, "SPRD",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_sprd, &spr_write_sprd,
> -                 0x00000000);
>   #endif
>   }
>   
> @@ -5781,6 +5771,17 @@ static void register_power9_book4_sprs(CPUPPCState *env)
>                        SPR_NOACCESS, SPR_NOACCESS,
>                        &spr_read_generic, &spr_write_generic,
>                        KVM_REG_PPC_WORT, 0);
> +    /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */
> +    spr_register_hv(env, SPR_POWER_SPRC, "SPRC",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, &spr_write_sprc,
> +                 0x00000000);
> +    spr_register_hv(env, SPR_POWER_SPRD, "SPRD",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_sprd, &spr_write_sprd,
> +                 0x00000000);
>   #endif
>   }
>   
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index fa47be2298..46ba3a5584 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -26,6 +26,7 @@
>   #include "qemu/main-loop.h"
>   #include "mmu-book3s-v3.h"
>   #include "hw/ppc/ppc.h"
> +#include "hw/ppc/pnv_core.h"
>   
>   #include "helper_regs.h"
>   
> @@ -321,11 +322,25 @@ void helper_store_sprc(CPUPPCState *env, target_ulong val)
>   
>   target_ulong helper_load_sprd(CPUPPCState *env)
>   {
> +    PowerPCCPU *cpu = env_archcpu(env);
> +    PnvCore *pc = pnv_cpu_state(cpu)->core;

We may want to avoid creating local variable cpu here also like previous 
patches.

However, is this helper meant to be accessible for spapr as well ?

>       target_ulong sprc = env->spr[SPR_POWER_SPRC];
>   
> -    switch (sprc & 0x3c0) {
> -    case 0: /* SCRATCH0-7 */
> -        return env->scratch[(sprc >> 3) & 0x7];
> +    switch (sprc & 0x3e0) {
> +    case 0: /* SCRATCH0-3 */
> +    case 1: /* SCRATCH4-7 */
> +        return pc->scratch[(sprc >> 3) & 0x7];

If so, will pc be uninitialized in case of spapr ?

> +    case 0x1e0: /* core thread state */
> +        if (env->excp_model == POWERPC_EXCP_POWER9) {
> +            /*
> +             * Only implement for POWER9 because skiboot uses it to check
> +             * big-core mode. Other bits are unimplemented so we would
> +             * prefer to get unimplemented message on POWER10 if it were
> +             * used.
> +             */
> +            return 0;
> +        }
> +        /* fallthru */
>       default:
>           qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x"
>                                     TARGET_FMT_lx"\n", sprc);
> @@ -334,41 +349,27 @@ target_ulong helper_load_sprd(CPUPPCState *env)
>       return 0;
>   }
>   
> -static void do_store_scratch(CPUPPCState *env, int nr, target_ulong val)
> -{
> -    CPUState *cs = env_cpu(env);
> -    CPUState *ccs;
> -    uint32_t nr_threads = cs->nr_threads;
> -
> -    /*
> -     * Log stores to SCRATCH, because some firmware uses these for debugging
> -     * and logging, but they would normally be read by the BMC, which is
> -     * not implemented in QEMU yet. This gives a way to get at the information.
> -     * Could also dump these upon checkstop.
> -     */
> -    qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr);
> -
> -    if (nr_threads == 1) {
> -        env->scratch[nr] = val;
> -        return;
> -    }
> -
> -    THREAD_SIBLING_FOREACH(cs, ccs) {
> -        CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;
> -        cenv->scratch[nr] = val;
> -    }
> -}
> -
>   void helper_store_sprd(CPUPPCState *env, target_ulong val)
>   {
>       target_ulong sprc = env->spr[SPR_POWER_SPRC];
> -
> -    switch (sprc & 0x3c0) {
> -    case 0: /* SCRATCH0-7 */
> -        do_store_scratch(env, (sprc >> 3) & 0x7, val);
> +    PowerPCCPU *cpu = env_archcpu(env);
> +    PnvCore *pc = pnv_cpu_state(cpu)->core;

Ditto?

> +
> +    switch (sprc & 0x3e0) {
> +    case 0: /* SCRATCH0-3 */
> +    case 1: /* SCRATCH4-7 */
> +        /*
> +         * Log stores to SCRATCH, because some firmware uses these for
> +         * debugging and logging, but they would normally be read by the BMC,
> +	 * which is not implemented in QEMU yet. This gives a way to get at the
> +	 * information. Could also dump these upon checkstop.
> +         */
> +        int nr = (sprc >> 3) & 0x7;
> +        qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr);
> +        pc->scratch[nr] = val;

regards,
Harsh
>           break;
>       default:
> -        qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x"
> +        qemu_log_mask(LOG_UNIMP, "mtSPRD: Unimplemented SPRC:0x"
>                                     TARGET_FMT_lx"\n", sprc);
>           break;
>       }

On Tue May 28, 2024 at 4:50 PM AEST, Harsh Prateek Bora wrote:
>
> Hi Nick,
>
> On 5/26/24 17:56, Nicholas Piggin wrote:
> > SPRC/SPRD were recently added to all BookS CPUs supported, but
> > they are only tested on POWER9 and POWER10, so restrict them to
> > those CPUs.
> > 
>
> Hope you mean to restrict to P9/10 for both spapr and pnv or just pnv ?

For pnv, but they are hypervisor registers so they can not be
accessed with spapr.

[...]

> > @@ -321,11 +322,25 @@ void helper_store_sprc(CPUPPCState *env, target_ulong val)
> >   
> >   target_ulong helper_load_sprd(CPUPPCState *env)
> >   {
> > +    PowerPCCPU *cpu = env_archcpu(env);
> > +    PnvCore *pc = pnv_cpu_state(cpu)->core;
>
> We may want to avoid creating local variable cpu here also like previous 
> patches.

Since we have a maze of pointers and types, sometimes I like to
write the types down, but maybe that's just me :P

> However, is this helper meant to be accessible for spapr as well ?

Right, it's not. I *think* it should be okay to do this since it
should never be reached by spapr.

Thanks,
Nick