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Thu, 9 May 2024 12:47:30 GMT Received: from smtpav01.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F242A58061; Thu, 9 May 2024 12:47:27 +0000 (GMT) Received: from smtpav01.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A35AD58057; Thu, 9 May 2024 12:47:27 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav01.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 9 May 2024 12:47:27 +0000 (GMT) From: Saif Abrar To: kbusch@kernel.org, its@irrelevant.dk, foss@defmacro.it Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, npiggin@gmail.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH] hw/nvme: Add CLI options for PCI vendor/device IDs and IEEE-OUI ID Date: Thu, 9 May 2024 07:47:23 -0500 Message-Id: <20240509124723.3930-1-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Eyw-x0NdaLd47T5iftBUftfj0eapzEpI X-Proofpoint-GUID: gvU4qIRM4CspPjuQd_hDdmV5rxKQmTIR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-09_06,2024-05-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1011 bulkscore=0 impostorscore=0 spamscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405090085 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add CLI options for user specified - PCI vendor, device, subsystem vendor and subsystem IDs - IEEE-OUI ID e.g. PCI IDs to be specified as follows: -device nvme,id_vendor=0xABCD,id_device=0xA0B0,id_subsys_vendor=0xEF00,id_subsys=0xEF01 IEEE-OUI ID (Identify Controller bytes 75:73) is to be specified in LE format. (e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD, Byte[75]=0xAB). Signed-off-by: Saif Abrar --- hw/nvme/nvme.h | 5 +++++ hw/nvme/ctrl.c | 44 ++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 45 insertions(+), 4 deletions(-) diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index bed8191bd5..6e19a479d1 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -537,6 +537,11 @@ typedef struct NvmeParams { uint8_t sriov_max_vq_per_vf; uint8_t sriov_max_vi_per_vf; bool msix_exclusive_bar; + uint16_t id_vendor; + uint16_t id_device; + uint16_t id_subsys_vendor; + uint16_t id_subsys; + uint32_t ieee_oui; } NvmeParams; typedef struct NvmeCtrl { diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 127c3d2383..35aeb48e0b 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8050,8 +8050,9 @@ out: static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset) { - uint16_t vf_dev_id = n->params.use_intel_id ? - PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME; + uint16_t vf_dev_id = n->params.id_device ? n->params.id_device : + (n->params.use_intel_id ? + PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME); NvmePriCtrlCap *cap = &n->pri_ctrl_cap; uint64_t bar_size = nvme_mbar_size(le16_to_cpu(cap->vqfrsm), le16_to_cpu(cap->vifrsm), @@ -8098,7 +8099,13 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) pci_conf[PCI_INTERRUPT_PIN] = 1; pci_config_set_prog_interface(pci_conf, 0x2); - if (n->params.use_intel_id) { + if (n->params.id_vendor) { + pci_config_set_vendor_id(pci_conf, n->params.id_vendor); + pci_config_set_device_id(pci_conf, n->params.id_device); + pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, + n->params.id_subsys_vendor); + pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, n->params.id_subsys); + } else if (n->params.use_intel_id) { pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_NVME); } else { @@ -8206,7 +8213,11 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) id->rab = 6; - if (n->params.use_intel_id) { + if (n->params.ieee_oui) { + id->ieee[0] = extract32(n->params.ieee_oui, 0, 8); + id->ieee[1] = extract32(n->params.ieee_oui, 8, 8); + id->ieee[2] = extract32(n->params.ieee_oui, 16, 8); + } else if (n->params.use_intel_id) { id->ieee[0] = 0xb3; id->ieee[1] = 0x02; id->ieee[2] = 0x00; @@ -8419,6 +8430,24 @@ static void nvme_exit(PCIDevice *pci_dev) memory_region_del_subregion(&n->bar0, &n->iomem); } +static void nvme_prop_ieee_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + Property *prop = opaque; + uint32_t *val = object_field_prop_ptr(obj, prop); + if (!visit_type_uint32(v, name, val, errp)) { + return; + } +} + +static const PropertyInfo nvme_prop_ieee = { + .name = "uint32", + .description = "IEEE OUI: Identify Controller bytes 75:73\ + in LE format. (e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD,\ + Byte[75]=0xAB)", + .set = nvme_prop_ieee_set, +}; + static Property nvme_props[] = { DEFINE_BLOCK_PROPERTIES(NvmeCtrl, namespace.blkconf), DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmr.dev, TYPE_MEMORY_BACKEND, @@ -8451,6 +8480,13 @@ static Property nvme_props[] = { params.sriov_max_vq_per_vf, 0), DEFINE_PROP_BOOL("msix-exclusive-bar", NvmeCtrl, params.msix_exclusive_bar, false), + DEFINE_PROP_UINT16("id_vendor", NvmeCtrl, params.id_vendor, 0), + DEFINE_PROP_UINT16("id_device", NvmeCtrl, params.id_device, 0), + DEFINE_PROP_UINT16("id_subsys_vendor", NvmeCtrl, + params.id_subsys_vendor, 0), + DEFINE_PROP_UINT16("id_subsys", NvmeCtrl, params.id_subsys, 0), + DEFINE_PROP("ieee_oui", NvmeCtrl, params.ieee_oui, nvme_prop_ieee, + uint32_t), DEFINE_PROP_END_OF_LIST(), };