| Message ID | 20240426110023.733309-2-adityag@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | Power11 support for QEMU | expand |
Hello Aditya On 4/26/24 13:00, Aditya Gupta wrote: > Add base support for "--cpu power11" in QEMU. > > Power11 core is same as Power10, hence reuse functions defined for > Power10. Power11 uses the same ISA it seems. What's the value then ? > > Cc: Cédric Le Goater <clg@kaod.org> > Cc: Daniel Henrique Barboza <danielhb413@gmail.com> > Cc: David Gibson <david@gibson.dropbear.id.au> > Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com> > Cc: Nicholas Piggin <npiggin@gmail.com> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> > --- > docs/system/ppc/pseries.rst | 6 +-- > hw/ppc/spapr_cpu_core.c | 1 + I would separate the CPU target code adding support for a new POWER Processor from the machine code (pseries). > target/ppc/compat.c | 7 +++ > target/ppc/cpu-models.c | 2 + > target/ppc/cpu-models.h | 2 + > target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++++++ > 6 files changed, 114 insertions(+), 3 deletions(-) > > diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst > index a876d897b6e4..3277564b34c2 100644 > --- a/docs/system/ppc/pseries.rst > +++ b/docs/system/ppc/pseries.rst > @@ -15,9 +15,9 @@ Supported devices > ================= > > * Multi processor support for many Power processors generations: POWER7, > - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, > - but its state is unknown. > - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) > + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+ > + exists, but its state is unknown. The POWER5+ pseries machine seems functionnal with SLOF (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth to mention (for AIX users) in another patch. > + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11) > * vPHB PCIe Host bridge. > * vscsi and vnet devices, compatible with the same devices available on a > PowerVM hypervisor with VIOS managing LPARs. > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index e7c9edd033c8..c6e85c031178 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), > + DEFINE_SPAPR_CPU_CORE_TYPE("power11"), > #ifdef CONFIG_KVM > DEFINE_SPAPR_CPU_CORE_TYPE("host"), > #endif > diff --git a/target/ppc/compat.c b/target/ppc/compat.c > index ebef2cccecf3..12dd8ae290ca 100644 > --- a/target/ppc/compat.c > +++ b/target/ppc/compat.c > @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = { > .pcr_level = PCR_COMPAT_3_10, > .max_vthreads = 8, > }, > + { /* POWER11, ISA3.10 */ > + .name = "power11", > + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, > + .pcr = PCR_COMPAT_3_10, > + .pcr_level = PCR_COMPAT_3_10, > + .max_vthreads = 8, > + }, > }; > > static const CompatInfo *compat_by_pvr(uint32_t pvr) > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > index f2301b43f78b..1870e69b63df 100644 > --- a/target/ppc/cpu-models.c > +++ b/target/ppc/cpu-models.c > @@ -734,6 +734,8 @@ > "POWER9 v2.2") > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > "POWER10 v2.0") > + POWERPC_DEF("power11", CPU_POWERPC_POWER11, POWER11, > + "POWER11") > #endif /* defined (TARGET_PPC64) */ > > /***************************************************************************/ > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > index 0229ef3a9a5c..a1b540c3aa9e 100644 > --- a/target/ppc/cpu-models.h > +++ b/target/ppc/cpu-models.h > @@ -354,6 +354,7 @@ enum { > CPU_POWERPC_POWER10_BASE = 0x00800000, > CPU_POWERPC_POWER10_DD1 = 0x00801100, > CPU_POWERPC_POWER10_DD20 = 0x00801200, > + CPU_POWERPC_POWER11 = 0x00821200, is that a DD2.2 PVR ? If so, It should be mentionned in the definition. Thanks, C. > CPU_POWERPC_970_v22 = 0x00390202, > CPU_POWERPC_970FX_v10 = 0x00391100, > CPU_POWERPC_970FX_v20 = 0x003C0200, > @@ -391,6 +392,7 @@ enum { > CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, > CPU_POWERPC_LOGICAL_3_00 = 0x0F000005, > CPU_POWERPC_LOGICAL_3_10 = 0x0F000006, > + CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007, > }; > > /* System version register (used on MPC 8xxx) */ > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 6d82f24c8756..17c159c8187b 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6655,6 +6655,105 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) > pcc->l1_icache_size = 0x8000; > } > > +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > +{ > + uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; > + uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; > + > + if (!best && (base == CPU_POWERPC_POWER11)) > + return true; > + > + if (base != pcc_base) > + return false; > + > + if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) > + return true; > + > + return false; > +} > + > +POWERPC_FAMILY(POWER11)(ObjectClass * oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); > + > + dc->fw_name = "PowerPC,POWER11"; > + dc->desc = "POWER11"; > + pcc->pvr_match = ppc_pvr_match_power11; > + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | > + PCR_COMPAT_3_00 | PCR_COMPAT_3_10; > + pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | > + PCR_COMPAT_2_06 | PCR_COMPAT_2_05; > + pcc->init_proc = init_proc_POWER10; > + pcc->check_pow = check_pow_nocheck; > + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | > + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | > + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | > + PPC_FLOAT_FRSQRTES | > + PPC_FLOAT_STFIWX | > + PPC_FLOAT_EXT | > + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | > + PPC_MEM_SYNC | PPC_MEM_EIEIO | > + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | > + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | > + PPC_SEGMENT_64B | PPC_SLBI | > + PPC_POPCNTB | PPC_POPCNTWD | > + PPC_CILDST; > + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | > + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | > + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | > + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | > + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | > + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | > + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; > + pcc->msr_mask = (1ull << MSR_SF) | > + (1ull << MSR_HV) | > + (1ull << MSR_TM) | > + (1ull << MSR_VR) | > + (1ull << MSR_VSX) | > + (1ull << MSR_EE) | > + (1ull << MSR_PR) | > + (1ull << MSR_FP) | > + (1ull << MSR_ME) | > + (1ull << MSR_FE0) | > + (1ull << MSR_SE) | > + (1ull << MSR_DE) | > + (1ull << MSR_FE1) | > + (1ull << MSR_IR) | > + (1ull << MSR_DR) | > + (1ull << MSR_PMM) | > + (1ull << MSR_RI) | > + (1ull << MSR_LE); > + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | > + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | > + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | > + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | > + LPCR_DEE | LPCR_OEE)) > + | LPCR_MER | LPCR_GTSE | LPCR_TC | > + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; > + /* DD2 adds an extra HAIL bit */ > + pcc->lpcr_mask |= LPCR_HAIL; > + > + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; > + pcc->mmu_model = POWERPC_MMU_3_00; > +#if !defined(CONFIG_USER_ONLY) > + /* segment page size remain the same */ > + pcc->hash64_opts = &ppc_hash64_opts_POWER7; > + pcc->radix_page_info = &POWER10_radix_page_info; > + pcc->lrg_decr_bits = 56; > +#endif > + pcc->excp_model = POWERPC_EXCP_POWER10; > + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; > + pcc->bfd_mach = bfd_mach_ppc64; > + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | > + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | > + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | > + POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; > + pcc->l1_dcache_size = 0x8000; > + pcc->l1_icache_size = 0x8000; > +} > + > #if !defined(CONFIG_USER_ONLY) > void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) > {
Hello Cédric, Thanks for your reviews. On Fri, Apr 26, 2024 at 04:27:04PM +0200, Cédric Le Goater wrote: > Hello Aditya > > On 4/26/24 13:00, Aditya Gupta wrote: > > Add base support for "--cpu power11" in QEMU. > > > > Power11 core is same as Power10, hence reuse functions defined for > > Power10. > > Power11 uses the same ISA it seems. What's the value then ? Yes, it uses the same ISA. But I added this option so we can have a Power11 PVR in QEMU, which should be identified as Power11 in skiboot and linux, hence defined Power11 cpu type, even though code here is almost same as Power10. > > > > > Cc: Cédric Le Goater <clg@kaod.org> > > Cc: Daniel Henrique Barboza <danielhb413@gmail.com> > > Cc: David Gibson <david@gibson.dropbear.id.au> > > Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> > > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> > > Cc: Madhavan Srinivasan <maddy@linux.ibm.com> > > Cc: Nicholas Piggin <npiggin@gmail.com> > > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> > > --- > > docs/system/ppc/pseries.rst | 6 +-- > > hw/ppc/spapr_cpu_core.c | 1 + > > > I would separate the CPU target code adding support for a new POWER > Processor from the machine code (pseries). Sure, I will split it in v3. > > > > target/ppc/compat.c | 7 +++ > > target/ppc/cpu-models.c | 2 + > > target/ppc/cpu-models.h | 2 + > > target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++++++ > > 6 files changed, 114 insertions(+), 3 deletions(-) > > > > diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst > > index a876d897b6e4..3277564b34c2 100644 > > --- a/docs/system/ppc/pseries.rst > > +++ b/docs/system/ppc/pseries.rst > > @@ -15,9 +15,9 @@ Supported devices > > ================= > > * Multi processor support for many Power processors generations: POWER7, > > - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, > > - but its state is unknown. > > - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) > > + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+ > > + exists, but its state is unknown. > > The POWER5+ pseries machine seems functionnal with SLOF > (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth > to mention (for AIX users) in another patch. > > > + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11) > > * vPHB PCIe Host bridge. > > * vscsi and vnet devices, compatible with the same devices available on a > > PowerVM hypervisor with VIOS managing LPARs. > > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > > index e7c9edd033c8..c6e85c031178 100644 > > --- a/hw/ppc/spapr_cpu_core.c > > +++ b/hw/ppc/spapr_cpu_core.c > > @@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { > > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), > > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), > > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), > > + DEFINE_SPAPR_CPU_CORE_TYPE("power11"), > > #ifdef CONFIG_KVM > > DEFINE_SPAPR_CPU_CORE_TYPE("host"), > > #endif > > diff --git a/target/ppc/compat.c b/target/ppc/compat.c > > index ebef2cccecf3..12dd8ae290ca 100644 > > --- a/target/ppc/compat.c > > +++ b/target/ppc/compat.c > > @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = { > > .pcr_level = PCR_COMPAT_3_10, > > .max_vthreads = 8, > > }, > > + { /* POWER11, ISA3.10 */ > > + .name = "power11", > > + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, > > + .pcr = PCR_COMPAT_3_10, > > + .pcr_level = PCR_COMPAT_3_10, > > + .max_vthreads = 8, > > + }, > > }; > > static const CompatInfo *compat_by_pvr(uint32_t pvr) > > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c > > index f2301b43f78b..1870e69b63df 100644 > > --- a/target/ppc/cpu-models.c > > +++ b/target/ppc/cpu-models.c > > @@ -734,6 +734,8 @@ > > "POWER9 v2.2") > > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, > > "POWER10 v2.0") > > + POWERPC_DEF("power11", CPU_POWERPC_POWER11, POWER11, > > + "POWER11") > > #endif /* defined (TARGET_PPC64) */ > > /***************************************************************************/ > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > > index 0229ef3a9a5c..a1b540c3aa9e 100644 > > --- a/target/ppc/cpu-models.h > > +++ b/target/ppc/cpu-models.h > > @@ -354,6 +354,7 @@ enum { > > CPU_POWERPC_POWER10_BASE = 0x00800000, > > CPU_POWERPC_POWER10_DD1 = 0x00801100, > > CPU_POWERPC_POWER10_DD20 = 0x00801200, > > + CPU_POWERPC_POWER11 = 0x00821200, > > is that a DD2.2 PVR ? If so, It should be mentionned in the definition. > Yes, I have kept the last 2 bytes same as P10 DD2. I will mention it above the line I have added it, in v3. Thanks, Aditya Gupta > > > Thanks, > > C. > > > > > CPU_POWERPC_970_v22 = 0x00390202, > > CPU_POWERPC_970FX_v10 = 0x00391100, > > CPU_POWERPC_970FX_v20 = 0x003C0200, > > @@ -391,6 +392,7 @@ enum { > > CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, > > CPU_POWERPC_LOGICAL_3_00 = 0x0F000005, > > CPU_POWERPC_LOGICAL_3_10 = 0x0F000006, > > + CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007, > > }; > > /* System version register (used on MPC 8xxx) */ > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > > index 6d82f24c8756..17c159c8187b 100644 > > --- a/target/ppc/cpu_init.c > > +++ b/target/ppc/cpu_init.c > > @@ -6655,6 +6655,105 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) > > pcc->l1_icache_size = 0x8000; > > } > > +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) > > +{ > > + uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; > > + uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; > > + > > + if (!best && (base == CPU_POWERPC_POWER11)) > > + return true; > > + > > + if (base != pcc_base) > > + return false; > > + > > + if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) > > + return true; > > + > > + return false; > > +} > > + > > +POWERPC_FAMILY(POWER11)(ObjectClass * oc, void *data) > > +{ > > + DeviceClass *dc = DEVICE_CLASS(oc); > > + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); > > + > > + dc->fw_name = "PowerPC,POWER11"; > > + dc->desc = "POWER11"; > > + pcc->pvr_match = ppc_pvr_match_power11; > > + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | > > + PCR_COMPAT_3_00 | PCR_COMPAT_3_10; > > + pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | > > + PCR_COMPAT_2_06 | PCR_COMPAT_2_05; > > + pcc->init_proc = init_proc_POWER10; > > + pcc->check_pow = check_pow_nocheck; > > + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | > > + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | > > + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | > > + PPC_FLOAT_FRSQRTES | > > + PPC_FLOAT_STFIWX | > > + PPC_FLOAT_EXT | > > + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | > > + PPC_MEM_SYNC | PPC_MEM_EIEIO | > > + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | > > + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | > > + PPC_SEGMENT_64B | PPC_SLBI | > > + PPC_POPCNTB | PPC_POPCNTWD | > > + PPC_CILDST; > > + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | > > + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | > > + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | > > + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | > > + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | > > + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > > + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | > > + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; > > + pcc->msr_mask = (1ull << MSR_SF) | > > + (1ull << MSR_HV) | > > + (1ull << MSR_TM) | > > + (1ull << MSR_VR) | > > + (1ull << MSR_VSX) | > > + (1ull << MSR_EE) | > > + (1ull << MSR_PR) | > > + (1ull << MSR_FP) | > > + (1ull << MSR_ME) | > > + (1ull << MSR_FE0) | > > + (1ull << MSR_SE) | > > + (1ull << MSR_DE) | > > + (1ull << MSR_FE1) | > > + (1ull << MSR_IR) | > > + (1ull << MSR_DR) | > > + (1ull << MSR_PMM) | > > + (1ull << MSR_RI) | > > + (1ull << MSR_LE); > > + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | > > + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | > > + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | > > + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | > > + LPCR_DEE | LPCR_OEE)) > > + | LPCR_MER | LPCR_GTSE | LPCR_TC | > > + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; > > + /* DD2 adds an extra HAIL bit */ > > + pcc->lpcr_mask |= LPCR_HAIL; > > + > > + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; > > + pcc->mmu_model = POWERPC_MMU_3_00; > > +#if !defined(CONFIG_USER_ONLY) > > + /* segment page size remain the same */ > > + pcc->hash64_opts = &ppc_hash64_opts_POWER7; > > + pcc->radix_page_info = &POWER10_radix_page_info; > > + pcc->lrg_decr_bits = 56; > > +#endif > > + pcc->excp_model = POWERPC_EXCP_POWER10; > > + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; > > + pcc->bfd_mach = bfd_mach_ppc64; > > + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | > > + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | > > + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | > > + POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; > > + pcc->l1_dcache_size = 0x8000; > > + pcc->l1_icache_size = 0x8000; > > +} > > + > > #if !defined(CONFIG_USER_ONLY) > > void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) > > { >
Hello Cédric, > > diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst > > index a876d897b6e4..3277564b34c2 100644 > > --- a/docs/system/ppc/pseries.rst > > +++ b/docs/system/ppc/pseries.rst > > @@ -15,9 +15,9 @@ Supported devices > > ================= > > * Multi processor support for many Power processors generations: POWER7, > > - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, > > - but its state is unknown. > > - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) > > + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+ > > + exists, but its state is unknown. > > The POWER5+ pseries machine seems functionnal with SLOF > (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth > to mention (for AIX users) in another patch. Sure, thanks for pointing this, will add these changes in a separate patch. There were some points in 'powernv' docs, that might need updating: Quoting lines from docs/system/ppc/powernv.rst: > Missing devices > --------------- > > A lot is missing, among which : > > * I2C controllers (yet to be merged). > * NPU/NPU2/NPU3 controllers. > * EEH support for PCIe Host bridge controllers. > * NX controller. > * VAS controller. > * chipTOD (Time Of Day). > * Self Boot Engine (SBE). > * FSI bus. I can see that 'chipTOD' was added in commit 9a69950feb098. I2C mentions yet to merge, is it merged yet ? I will check whether this needs updating, but might do it in a separate patch than this series. Thanks, - Aditya Gupta > > > + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11) > > * vPHB PCIe Host bridge. > > * vscsi and vnet devices, compatible with the same devices available on a > > PowerVM hypervisor with VIOS managing LPARs.
On 4/26/24 19:12, Aditya Gupta wrote: > Hello Cédric, > >>> diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst >>> index a876d897b6e4..3277564b34c2 100644 >>> --- a/docs/system/ppc/pseries.rst >>> +++ b/docs/system/ppc/pseries.rst >>> @@ -15,9 +15,9 @@ Supported devices >>> ================= >>> * Multi processor support for many Power processors generations: POWER7, >>> - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, >>> - but its state is unknown. >>> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) >>> + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+ >>> + exists, but its state is unknown. >> >> The POWER5+ pseries machine seems functionnal with SLOF >> (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth >> to mention (for AIX users) in another patch. > > Sure, thanks for pointing this, will add these changes in a separate > patch. > > There were some points in 'powernv' docs, that might need updating: > > Quoting lines from docs/system/ppc/powernv.rst: > >> Missing devices >> --------------- >> >> A lot is missing, among which : >> >> * I2C controllers (yet to be merged). >> * NPU/NPU2/NPU3 controllers. >> * EEH support for PCIe Host bridge controllers. >> * NX controller. >> * VAS controller. >> * chipTOD (Time Of Day). >> * Self Boot Engine (SBE). >> * FSI bus. > > I can see that 'chipTOD' was added in commit 9a69950feb098. I2C mentions > yet to merge, is it merged yet ? yes. > > I will check whether this needs updating, but might do it in a separate > patch than this series. Thanks,
On 4/26/24 19:05, Aditya Gupta wrote: > Hello Cédric, > > Thanks for your reviews. > > On Fri, Apr 26, 2024 at 04:27:04PM +0200, Cédric Le Goater wrote: >> Hello Aditya >> >> On 4/26/24 13:00, Aditya Gupta wrote: >>> Add base support for "--cpu power11" in QEMU. >>> >>> Power11 core is same as Power10, hence reuse functions defined for >>> Power10. >> >> Power11 uses the same ISA it seems. What's the value then ? > > Yes, it uses the same ISA. But I added this option so we can have a > Power11 PVR in QEMU, which should be identified as Power11 in skiboot > and linux, hence defined Power11 cpu type, even though code here is > almost same as Power10. > >> >>> >>> Cc: Cédric Le Goater <clg@kaod.org> >>> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> >>> Cc: David Gibson <david@gibson.dropbear.id.au> >>> Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> >>> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> >>> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> >>> Cc: Nicholas Piggin <npiggin@gmail.com> >>> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> >>> --- >>> docs/system/ppc/pseries.rst | 6 +-- >>> hw/ppc/spapr_cpu_core.c | 1 + >> >> >> I would separate the CPU target code adding support for a new POWER >> Processor from the machine code (pseries). > > Sure, I will split it in v3. > >> >> >>> target/ppc/compat.c | 7 +++ >>> target/ppc/cpu-models.c | 2 + >>> target/ppc/cpu-models.h | 2 + >>> target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++++++ >>> 6 files changed, 114 insertions(+), 3 deletions(-) >>> >>> diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst >>> index a876d897b6e4..3277564b34c2 100644 >>> --- a/docs/system/ppc/pseries.rst >>> +++ b/docs/system/ppc/pseries.rst >>> @@ -15,9 +15,9 @@ Supported devices >>> ================= >>> * Multi processor support for many Power processors generations: POWER7, >>> - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, >>> - but its state is unknown. >>> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) >>> + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+ >>> + exists, but its state is unknown. >> >> The POWER5+ pseries machine seems functionnal with SLOF >> (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth >> to mention (for AIX users) in another patch. >> >>> + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11) >>> * vPHB PCIe Host bridge. >>> * vscsi and vnet devices, compatible with the same devices available on a >>> PowerVM hypervisor with VIOS managing LPARs. >>> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c >>> index e7c9edd033c8..c6e85c031178 100644 >>> --- a/hw/ppc/spapr_cpu_core.c >>> +++ b/hw/ppc/spapr_cpu_core.c >>> @@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { >>> DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), >>> DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), >>> DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), >>> + DEFINE_SPAPR_CPU_CORE_TYPE("power11"), >>> #ifdef CONFIG_KVM >>> DEFINE_SPAPR_CPU_CORE_TYPE("host"), >>> #endif >>> diff --git a/target/ppc/compat.c b/target/ppc/compat.c >>> index ebef2cccecf3..12dd8ae290ca 100644 >>> --- a/target/ppc/compat.c >>> +++ b/target/ppc/compat.c >>> @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = { >>> .pcr_level = PCR_COMPAT_3_10, >>> .max_vthreads = 8, >>> }, >>> + { /* POWER11, ISA3.10 */ >>> + .name = "power11", >>> + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, >>> + .pcr = PCR_COMPAT_3_10, >>> + .pcr_level = PCR_COMPAT_3_10, >>> + .max_vthreads = 8, >>> + }, >>> }; >>> static const CompatInfo *compat_by_pvr(uint32_t pvr) >>> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c >>> index f2301b43f78b..1870e69b63df 100644 >>> --- a/target/ppc/cpu-models.c >>> +++ b/target/ppc/cpu-models.c >>> @@ -734,6 +734,8 @@ >>> "POWER9 v2.2") >>> POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, >>> "POWER10 v2.0") >>> + POWERPC_DEF("power11", CPU_POWERPC_POWER11, POWER11, >>> + "POWER11") >>> #endif /* defined (TARGET_PPC64) */ >>> /***************************************************************************/ >>> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h >>> index 0229ef3a9a5c..a1b540c3aa9e 100644 >>> --- a/target/ppc/cpu-models.h >>> +++ b/target/ppc/cpu-models.h >>> @@ -354,6 +354,7 @@ enum { >>> CPU_POWERPC_POWER10_BASE = 0x00800000, >>> CPU_POWERPC_POWER10_DD1 = 0x00801100, >>> CPU_POWERPC_POWER10_DD20 = 0x00801200, >>> + CPU_POWERPC_POWER11 = 0x00821200, >> >> is that a DD2.2 PVR ? If so, It should be mentionned in the definition. >> > > Yes, I have kept the last 2 bytes same as P10 DD2. I will mention it > above the line I have added it, in v3. Skiboot reports : [ 0.121234172,6] P11 DD1.00 detected C.
> > Quoting lines from docs/system/ppc/powernv.rst: > > > > > Missing devices > > > --------------- > > > > > > A lot is missing, among which : > > > > > > * I2C controllers (yet to be merged). > > > * NPU/NPU2/NPU3 controllers. > > > * EEH support for PCIe Host bridge controllers. > > > * NX controller. > > > * VAS controller. > > > * chipTOD (Time Of Day). > > > * Self Boot Engine (SBE). > > > * FSI bus. > > > > I can see that 'chipTOD' was added in commit 9a69950feb098. I2C mentions > > yet to merge, is it merged yet ? > > yes. Thanks for confirming Cédric ! - Aditya Gupta > > > > > I will check whether this needs updating, but might do it in a separate > > patch than this series. > > Thanks, > >
Hi Cédric, > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h >>>> index 0229ef3a9a5c..a1b540c3aa9e 100644 >>>> --- a/target/ppc/cpu-models.h >>>> +++ b/target/ppc/cpu-models.h >>>> @@ -354,6 +354,7 @@ enum { >>>> CPU_POWERPC_POWER10_BASE = 0x00800000, >>>> CPU_POWERPC_POWER10_DD1 = 0x00801100, >>>> CPU_POWERPC_POWER10_DD20 = 0x00801200, >>>> + CPU_POWERPC_POWER11 = 0x00821200, >>> >>> is that a DD2.2 PVR ? If so, It should be mentionned in the definition. >>> >> >> Yes, I have kept the last 2 bytes same as P10 DD2. I will mention it >> above the line I have added it, in v3. > > Skiboot reports : > > [ 0.121234172,6] P11 DD1.00 detected > It is a DD2.0, with major revision = 0x2, and minor revision = 0. Might need some change in skiboot. Will post a v3 series with changes. Thanks, - Aditya Gupta > > C.
Hi Cédric, >> >> Skiboot reports : >> >> [ 0.121234172,6] P11 DD1.00 detected >> > It is a DD2.0, with major revision = 0x2, and minor revision = 0. > Might need some change in skiboot. Will post a v3 series with changes. > The issue was in QEMU, not skiboot. QEMU sets CFAM id for Power10 as DD1.0 (hw/ppc/pnv.c: 2093): k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ CFAM is same for Power11, and hence for both 'powernv10' and 'powernv11', skiboot shows DD1.0. It should be `0x220da04980000000` for DD2.0. Should I update the CFAM in a separate patch ? Thanks, Aditya Gupta > > Thanks, > > - Aditya Gupta > >> >> C.
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index a876d897b6e4..3277564b34c2 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -15,9 +15,9 @@ Supported devices ================= * Multi processor support for many Power processors generations: POWER7, - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, - but its state is unknown. - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+ + exists, but its state is unknown. + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11) * vPHB PCIe Host bridge. * vscsi and vnet devices, compatible with the same devices available on a PowerVM hypervisor with VIOS managing LPARs. diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index e7c9edd033c8..c6e85c031178 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), + DEFINE_SPAPR_CPU_CORE_TYPE("power11"), #ifdef CONFIG_KVM DEFINE_SPAPR_CPU_CORE_TYPE("host"), #endif diff --git a/target/ppc/compat.c b/target/ppc/compat.c index ebef2cccecf3..12dd8ae290ca 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = { .pcr_level = PCR_COMPAT_3_10, .max_vthreads = 8, }, + { /* POWER11, ISA3.10 */ + .name = "power11", + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS, + .pcr = PCR_COMPAT_3_10, + .pcr_level = PCR_COMPAT_3_10, + .max_vthreads = 8, + }, }; static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index f2301b43f78b..1870e69b63df 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -734,6 +734,8 @@ "POWER9 v2.2") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, "POWER10 v2.0") + POWERPC_DEF("power11", CPU_POWERPC_POWER11, POWER11, + "POWER11") #endif /* defined (TARGET_PPC64) */ /***************************************************************************/ diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a5c..a1b540c3aa9e 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -354,6 +354,7 @@ enum { CPU_POWERPC_POWER10_BASE = 0x00800000, CPU_POWERPC_POWER10_DD1 = 0x00801100, CPU_POWERPC_POWER10_DD20 = 0x00801200, + CPU_POWERPC_POWER11 = 0x00821200, CPU_POWERPC_970_v22 = 0x00390202, CPU_POWERPC_970FX_v10 = 0x00391100, CPU_POWERPC_970FX_v20 = 0x003C0200, @@ -391,6 +392,7 @@ enum { CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, CPU_POWERPC_LOGICAL_3_00 = 0x0F000005, CPU_POWERPC_LOGICAL_3_10 = 0x0F000006, + CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007, }; /* System version register (used on MPC 8xxx) */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6d82f24c8756..17c159c8187b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6655,6 +6655,105 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_icache_size = 0x8000; } +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) +{ + uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; + uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; + + if (!best && (base == CPU_POWERPC_POWER11)) + return true; + + if (base != pcc_base) + return false; + + if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) + return true; + + return false; +} + +POWERPC_FAMILY(POWER11)(ObjectClass * oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER11"; + dc->desc = "POWER11"; + pcc->pvr_match = ppc_pvr_match_power11; + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | + PCR_COMPAT_3_00 | PCR_COMPAT_3_10; + pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->init_proc = init_proc_POWER10; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_HV) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) + | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + /* DD2 adds an extra HAIL bit */ + pcc->lpcr_mask |= LPCR_HAIL; + + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; + pcc->mmu_model = POWERPC_MMU_3_00; +#if !defined(CONFIG_USER_ONLY) + /* segment page size remain the same */ + pcc->hash64_opts = &ppc_hash64_opts_POWER7; + pcc->radix_page_info = &POWER10_radix_page_info; + pcc->lrg_decr_bits = 56; +#endif + pcc->excp_model = POWERPC_EXCP_POWER10; + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) {
Add base support for "--cpu power11" in QEMU. Power11 core is same as Power10, hence reuse functions defined for Power10. Cc: Cédric Le Goater <clg@kaod.org> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Harsh Prateek Bora <harshpb@linux.ibm.com> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> --- docs/system/ppc/pseries.rst | 6 +-- hw/ppc/spapr_cpu_core.c | 1 + target/ppc/compat.c | 7 +++ target/ppc/cpu-models.c | 2 + target/ppc/cpu-models.h | 2 + target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++++++ 6 files changed, 114 insertions(+), 3 deletions(-)