@@ -106,6 +106,7 @@ typedef struct DisasContext {
bool cfg_vta_all_1s;
bool vstart_eq_zero;
bool vl_eq_vlmax;
+ uint16_t mlen;
CPUState *cs;
TCGv zero;
/* PointerMasking extension */
@@ -1207,6 +1208,9 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
ctx->decoders = cpu->decoders;
+ if (cpu->cfg.ext_xtheadvector) {
+ ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
+ }
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
The mask register layout of XTheadVector is different from that of RVV1.0. For RVV1.0, the mask bits for element i are located in bit[i] of the mask register. While for XTheadVector, the mask bits for element i are located bit[MLEN*i] of the mask register. (MLEN = SEW/LMUL) So we add mlen in DisasContext to indicate the mask bit and reduce the calculation of mlen. Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com> --- target/riscv/translate.c | 4 ++++ 1 file changed, 4 insertions(+)