@@ -2197,3 +2197,16 @@ DEF_HELPER_5(th_vfclass_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(th_vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_5(th_vfcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_xu_f_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_x_f_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32)
@@ -2191,16 +2191,18 @@ static bool trans_th_vfmv_v_f(DisasContext *s, arg_th_vfmv_v_f *a)
return false;
}
+/* Single-Width Floating-Point/Integer Type-Convert Instructions */
+GEN_OPFV_TRANS_TH(th_vfcvt_xu_f_v, opfv_check_th)
+GEN_OPFV_TRANS_TH(th_vfcvt_x_f_v, opfv_check_th)
+GEN_OPFV_TRANS_TH(th_vfcvt_f_xu_v, opfv_check_th)
+GEN_OPFV_TRANS_TH(th_vfcvt_f_x_v, opfv_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vfcvt_xu_f_v)
-TH_TRANS_STUB(th_vfcvt_x_f_v)
-TH_TRANS_STUB(th_vfcvt_f_xu_v)
-TH_TRANS_STUB(th_vfcvt_f_x_v)
TH_TRANS_STUB(th_vfwcvt_xu_f_v)
TH_TRANS_STUB(th_vfwcvt_x_f_v)
TH_TRANS_STUB(th_vfwcvt_f_xu_v)
@@ -3205,3 +3205,36 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
GEN_VFMERGE_VF_TH(th_vfmerge_vfm_h, int16_t, H2, clearh_th)
GEN_VFMERGE_VF_TH(th_vfmerge_vfm_w, int32_t, H4, clearl_th)
GEN_VFMERGE_VF_TH(th_vfmerge_vfm_d, int64_t, H8, clearq_th)
+
+/* Single-Width Floating-Point/Integer Type-Convert Instructions */
+/* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
+THCALL(TH_OPFVV1, th_vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
+THCALL(TH_OPFVV1, th_vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
+THCALL(TH_OPFVV1, th_vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
+GEN_TH_V_ENV(th_vfcvt_xu_f_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfcvt_xu_f_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfcvt_xu_f_v_d, 8, 8, clearq_th)
+
+/* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
+THCALL(TH_OPFVV1, th_vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
+THCALL(TH_OPFVV1, th_vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
+THCALL(TH_OPFVV1, th_vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
+GEN_TH_V_ENV(th_vfcvt_x_f_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfcvt_x_f_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfcvt_x_f_v_d, 8, 8, clearq_th)
+
+/* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
+THCALL(TH_OPFVV1, th_vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
+THCALL(TH_OPFVV1, th_vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
+THCALL(TH_OPFVV1, th_vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
+GEN_TH_V_ENV(th_vfcvt_f_xu_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfcvt_f_xu_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfcvt_f_xu_v_d, 8, 8, clearq_th)
+
+/* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
+THCALL(TH_OPFVV1, th_vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
+THCALL(TH_OPFVV1, th_vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
+THCALL(TH_OPFVV1, th_vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
+GEN_TH_V_ENV(th_vfcvt_f_x_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfcvt_f_x_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfcvt_f_x_v_d, 8, 8, clearq_th)
Compared to RVV1.0, XTheadVector lacks .rtz instructions, which specify the rounding mode of rounding to zero. Except of lack of similar instructions, the instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com> --- target/riscv/helper.h | 13 ++++++++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 10 +++--- target/riscv/xtheadvector_helper.c | 33 +++++++++++++++++++ 3 files changed, 52 insertions(+), 4 deletions(-)