@@ -545,8 +545,8 @@ static void rv64_thead_c906_cpu_init(Object *obj)
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
- th_register_custom_csrs(cpu);
#endif
+ th_register_custom_csrs(cpu);
/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.pmp = true;
@@ -12,6 +12,7 @@ riscv_ss.add(files(
'cpu.c',
'cpu_helper.c',
'csr.c',
+ 'th_csr.c',
'fpu_helper.c',
'gdbstub.c',
'op_helper.c',
@@ -33,7 +34,6 @@ riscv_system_ss.add(files(
'monitor.c',
'machine.c',
'pmu.c',
- 'th_csr.c',
'time_helper.c',
'riscv-qmp-cmds.c',
))
@@ -33,6 +33,15 @@ typedef struct {
riscv_csr_operations csr_ops;
} riscv_csr;
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+ if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+ return -1;
+ }
+ return 0;
+}
+
+#if !defined(CONFIG_USER_ONLY)
static RISCVException s_mode_csr(CPURISCVState *env, int csrno)
{
if (env->debugger)
@@ -44,13 +53,6 @@ static RISCVException s_mode_csr(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
-static int test_thead_mvendorid(RISCVCPU *cpu)
-{
- if (cpu->cfg.mvendorid != THEAD_VENDOR_ID)
- return -1;
- return 0;
-}
-
static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -58,13 +60,16 @@ static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
*val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
return RISCV_EXCP_NONE;
}
+#endif
static riscv_csr th_csr_list[] = {
+#if !defined(CONFIG_USER_ONLY)
{
.csrno = CSR_TH_SXSTATUS,
.insertion_test = test_thead_mvendorid,
.csr_ops = { "th.sxstatus", s_mode_csr, read_th_sxstatus }
- }
+ },
+#endif
};
void th_register_custom_csrs(RISCVCPU *cpu)
The former patch added th_csr.c to add th.sxstatus csr for XTheadMaee. However, it can only support system-mode vendor csrs. In this patch, I change the way of compiling th_csr.c and calling the function th_register_custom_csrs, using '#if !defined(CONFIG_USER_ONLY)' in th_csr.c to support both user-mode and system-mode vendor csrs. Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com> --- target/riscv/cpu.c | 2 +- target/riscv/meson.build | 2 +- target/riscv/th_csr.c | 21 +++++++++++++-------- 3 files changed, 15 insertions(+), 10 deletions(-)