| Message ID | 20240320072709.1043227-5-max.chou@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions | expand |
On 3/20/24 04:25, Max Chou wrote: > If the checking functions check both the single and double width > operators at the same time, then the single width operator checking > functions (require_rvf[min]) will check whether the SEW is 8. > > Signed-off-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------ > 1 file changed, 4 insertions(+), 12 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 19059fea5f..08c22f48cb 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2333,7 +2333,6 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) > return require_rvv(s) && > require_rvf(s) && > require_scale_rvf(s) && > - (s->sew != MO_8) && > vext_check_isa_ill(s) && > vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); > } > @@ -2373,7 +2372,6 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) > return require_rvv(s) && > require_rvf(s) && > require_scale_rvf(s) && > - (s->sew != MO_8) && > vext_check_isa_ill(s) && > vext_check_ds(s, a->rd, a->rs2, a->vm); > } > @@ -2406,7 +2404,6 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) > return require_rvv(s) && > require_rvf(s) && > require_scale_rvf(s) && > - (s->sew != MO_8) && > vext_check_isa_ill(s) && > vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); > } > @@ -2446,7 +2443,6 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) > return require_rvv(s) && > require_rvf(s) && > require_scale_rvf(s) && > - (s->sew != MO_8) && > vext_check_isa_ill(s) && > vext_check_dd(s, a->rd, a->rs2, a->vm); > } > @@ -2704,8 +2700,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) > { > return opfv_widen_check(s, a) && > require_rvfmin(s) && > - require_scale_rvfmin(s) && > - (s->sew != MO_8); > + require_scale_rvfmin(s); > } > > #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \ > @@ -2810,16 +2805,14 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) > { > return opfv_narrow_check(s, a) && > require_rvfmin(s) && > - require_scale_rvfmin(s) && > - (s->sew != MO_8); > + require_scale_rvfmin(s); > } > > static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) > { > return opfv_narrow_check(s, a) && > require_rvf(s) && > - require_scale_rvf(s) && > - (s->sew != MO_8); > + require_scale_rvf(s); > } > > #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ > @@ -2947,8 +2940,7 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) > { > return reduction_widen_check(s, a) && > require_rvf(s) && > - require_scale_rvf(s) && > - (s->sew != MO_8); > + require_scale_rvf(s); > } > > GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 19059fea5f..08c22f48cb 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2333,7 +2333,6 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2373,7 +2372,6 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_ds(s, a->rd, a->rs2, a->vm); } @@ -2406,7 +2404,6 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2446,7 +2443,6 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dd(s, a->rd, a->rs2, a->vm); } @@ -2704,8 +2700,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) { return opfv_widen_check(s, a) && require_rvfmin(s) && - require_scale_rvfmin(s) && - (s->sew != MO_8); + require_scale_rvfmin(s); } #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \ @@ -2810,16 +2805,14 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && require_rvfmin(s) && - require_scale_rvfmin(s) && - (s->sew != MO_8); + require_scale_rvfmin(s); } static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && require_rvf(s) && - require_scale_rvf(s) && - (s->sew != MO_8); + require_scale_rvf(s); } #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ @@ -2947,8 +2940,7 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_widen_check(s, a) && require_rvf(s) && - require_scale_rvf(s) && - (s->sew != MO_8); + require_scale_rvf(s); } GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
If the checking functions check both the single and double width operators at the same time, then the single width operator checking functions (require_rvf[min]) will check whether the SEW is 8. Signed-off-by: Max Chou <max.chou@sifive.com> --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-)