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([49.37.251.185]) by smtp.gmail.com with ESMTPSA id y7-20020a17090322c700b001dc6f7e794dsm1465859plg.16.2024.03.14.04.35.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 04:35:18 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: ajones@ventanamicro.com Subject: [PATCH v6 2/3] target/riscv: Expose sdtrig ISA extension Date: Thu, 14 Mar 2024 17:05:09 +0530 Message-Id: <20240314113510.477862-3-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314113510.477862-1-hchauhan@ventanamicro.com> References: <20240314113510.477862-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=hchauhan@ventanamicro.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled. The sdtrig extension may or may not be implemented in a system. Therefore, the -cpu rv64,sdtrig= option can be used to dynamically turn sdtrig extension on or off. Since, the sdtrig ISA extension is a superset of debug specification, disable the debug property when sdtrig is enabled. A warning is printed when this is done. By default, the sdtrig extension is disabled and debug property enabled as usual. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2602aae9f5..66c91fffd6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -175,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), @@ -1008,6 +1009,11 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY + if (!cpu->cfg.debug && cpu->cfg.ext_sdtrig) { + warn_report("Enabling 'debug' since 'sdtrig' is enabled."); + cpu->cfg.debug = true; + } + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } @@ -1480,6 +1486,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),