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Tue, 12 Mar 2024 06:14:59 -0700 (PDT) Received: from wheely.local0.net ([118.208.155.46]) by smtp.gmail.com with ESMTPSA id r15-20020aa78b8f000000b006e64f75c947sm6066084pfd.46.2024.03.12.06.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 06:14:58 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , David Gibson , Harsh Prateek Bora Subject: [PATCH v2 09/10] target/ppc: Prevent supervisor from modifying MSR[ME] Date: Tue, 12 Mar 2024 23:14:18 +1000 Message-ID: <20240312131419.2196845-10-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240312131419.2196845-1-npiggin@gmail.com> References: <20240312131419.2196845-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=npiggin@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Prevent guest state modifying the MSR[ME] bit. Per ISA: An attempt to modify MSR[ME] in privileged but non-hypervisor state is ignored (i.e., the bit is not changed). Reviewed-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/helper_regs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 410b39c231..25258986e3 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -264,6 +264,11 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) value &= ~MSR_HVB; value |= env->msr & MSR_HVB; } + /* Attempt to modify MSR[ME] in guest state is ignored */ + if (is_book3s_arch2x(env) && !(env->msr & MSR_HVB)) { + value &= ~(1 << MSR_ME); + value |= env->msr & (1 << MSR_ME); + } if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) { cpu_interrupt_exittb(cs); }