| Message ID | 20240307032327.4799-4-ltaylorsimpson@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | Clean up .new decode and scripts | expand |
> -----Original Message----- > From: Taylor Simpson <ltaylorsimpson@gmail.com> > Sent: Wednesday, March 6, 2024 9:23 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain <bcain@quicinc.com>; Matheus Bernardino (QUIC) > <quic_mathbern@quicinc.com>; Sid Manning <sidneym@quicinc.com>; > Marco Liebel (QUIC) <quic_mliebel@quicinc.com>; > richard.henderson@linaro.org; philmd@linaro.org; ale@rev.ng; anjo@rev.ng; > ltaylorsimpson@gmail.com > Subject: [PATCH v2 3/9] Hexagon (target/hexagon) Mark dest_idx in trans > functions > > WARNING: This email originated from outside of Qualcomm. Please be wary > of any links or attachments, and do not enable macros. > > Check that the value matches opcode_reginfo/opcode_wregs > > Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> > --- Reviewed-by: Brian Cain <bcain@quicinc.com> > target/hexagon/insn.h | 1 + > target/hexagon/decode.c | 2 ++ > target/hexagon/mmvec/decode_ext_mmvec.c | 2 ++ > target/hexagon/gen_trans_funcs.py | 6 ++++++ > 4 files changed, 11 insertions(+) > > diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h > index 36502bf056..a770379958 100644 > --- a/target/hexagon/insn.h > +++ b/target/hexagon/insn.h > @@ -40,6 +40,7 @@ struct Instruction { > uint32_t which_extended:1; /* If has an extender, which immediate */ > uint32_t new_value_producer_slot:4; > int32_t new_read_idx; > + int32_t dest_idx; > > bool part1; /* > * cmp-jumps are split into two insns. > diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c > index 4595e30384..a4d8500fea 100644 > --- a/target/hexagon/decode.c > +++ b/target/hexagon/decode.c > @@ -184,6 +184,8 @@ decode_fill_newvalue_regno(Packet *packet) > > /* Now patch up the consumer with the register number */ > dst_idx = dststr - opcode_reginfo[def_opcode]; > + g_assert(packet->insn[def_idx].dest_idx != -1 && > + packet->insn[def_idx].dest_idx == dst_idx); > packet->insn[i].regno[use_regidx] = > packet->insn[def_idx].regno[dst_idx]; > /* > diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c > b/target/hexagon/mmvec/decode_ext_mmvec.c > index e9007f5d71..c1320406df 100644 > --- a/target/hexagon/mmvec/decode_ext_mmvec.c > +++ b/target/hexagon/mmvec/decode_ext_mmvec.c > @@ -86,6 +86,8 @@ check_new_value(Packet *pkt) > /* still not there, we have a bad packet */ > g_assert_not_reached(); > } > + g_assert(pkt->insn[def_idx].dest_idx != -1 && > + pkt->insn[def_idx].dest_idx == dststr - reginfo); > int def_regnum = pkt->insn[def_idx].regno[dststr - reginfo]; > /* Now patch up the consumer with the register number */ > pkt->insn[i].regno[use_regidx] = def_regnum ^ def_oreg; > diff --git a/target/hexagon/gen_trans_funcs.py > b/target/hexagon/gen_trans_funcs.py > index 8acecdb993..1201172dda 100755 > --- a/target/hexagon/gen_trans_funcs.py > +++ b/target/hexagon/gen_trans_funcs.py > @@ -69,6 +69,7 @@ def mark_which_imm_extended(f, tag): > ## insn->regno[1] = args->Rs; > ## insn->regno[2] = args->Rt; > ## insn->new_read_idx = -1; > +## insn->dest_idx = 0; > ## return true; > ## } > ## > @@ -86,6 +87,7 @@ def gen_trans_funcs(f): > """)) > > new_read_idx = -1 > + dest_idx = -1 > for regno, (reg_type, reg_id, *_) in enumerate(regs): > reg = hex_common.get_register(tag, reg_type, reg_id) > f.write(code_fmt(f"""\ > @@ -93,6 +95,9 @@ def gen_trans_funcs(f): > """)) > if reg.is_read() and reg.is_new(): > new_read_idx = regno > + # dest_idx should be the first destination, so check for -1 > + if reg.is_written() and dest_idx == -1: > + dest_idx = regno > > if len(imms) != 0: > mark_which_imm_extended(f, tag) > @@ -115,6 +120,7 @@ def gen_trans_funcs(f): > > f.write(code_fmt(f"""\ > insn->new_read_idx = {new_read_idx}; > + insn->dest_idx = {dest_idx}; > """)) > f.write(textwrap.dedent(f"""\ > return true; > -- > 2.34.1
diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h index 36502bf056..a770379958 100644 --- a/target/hexagon/insn.h +++ b/target/hexagon/insn.h @@ -40,6 +40,7 @@ struct Instruction { uint32_t which_extended:1; /* If has an extender, which immediate */ uint32_t new_value_producer_slot:4; int32_t new_read_idx; + int32_t dest_idx; bool part1; /* * cmp-jumps are split into two insns. diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 4595e30384..a4d8500fea 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -184,6 +184,8 @@ decode_fill_newvalue_regno(Packet *packet) /* Now patch up the consumer with the register number */ dst_idx = dststr - opcode_reginfo[def_opcode]; + g_assert(packet->insn[def_idx].dest_idx != -1 && + packet->insn[def_idx].dest_idx == dst_idx); packet->insn[i].regno[use_regidx] = packet->insn[def_idx].regno[dst_idx]; /* diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c b/target/hexagon/mmvec/decode_ext_mmvec.c index e9007f5d71..c1320406df 100644 --- a/target/hexagon/mmvec/decode_ext_mmvec.c +++ b/target/hexagon/mmvec/decode_ext_mmvec.c @@ -86,6 +86,8 @@ check_new_value(Packet *pkt) /* still not there, we have a bad packet */ g_assert_not_reached(); } + g_assert(pkt->insn[def_idx].dest_idx != -1 && + pkt->insn[def_idx].dest_idx == dststr - reginfo); int def_regnum = pkt->insn[def_idx].regno[dststr - reginfo]; /* Now patch up the consumer with the register number */ pkt->insn[i].regno[use_regidx] = def_regnum ^ def_oreg; diff --git a/target/hexagon/gen_trans_funcs.py b/target/hexagon/gen_trans_funcs.py index 8acecdb993..1201172dda 100755 --- a/target/hexagon/gen_trans_funcs.py +++ b/target/hexagon/gen_trans_funcs.py @@ -69,6 +69,7 @@ def mark_which_imm_extended(f, tag): ## insn->regno[1] = args->Rs; ## insn->regno[2] = args->Rt; ## insn->new_read_idx = -1; +## insn->dest_idx = 0; ## return true; ## } ## @@ -86,6 +87,7 @@ def gen_trans_funcs(f): """)) new_read_idx = -1 + dest_idx = -1 for regno, (reg_type, reg_id, *_) in enumerate(regs): reg = hex_common.get_register(tag, reg_type, reg_id) f.write(code_fmt(f"""\ @@ -93,6 +95,9 @@ def gen_trans_funcs(f): """)) if reg.is_read() and reg.is_new(): new_read_idx = regno + # dest_idx should be the first destination, so check for -1 + if reg.is_written() and dest_idx == -1: + dest_idx = regno if len(imms) != 0: mark_which_imm_extended(f, tag) @@ -115,6 +120,7 @@ def gen_trans_funcs(f): f.write(code_fmt(f"""\ insn->new_read_idx = {new_read_idx}; + insn->dest_idx = {dest_idx}; """)) f.write(textwrap.dedent(f"""\ return true;
Check that the value matches opcode_reginfo/opcode_wregs Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> --- target/hexagon/insn.h | 1 + target/hexagon/decode.c | 2 ++ target/hexagon/mmvec/decode_ext_mmvec.c | 2 ++ target/hexagon/gen_trans_funcs.py | 6 ++++++ 4 files changed, 11 insertions(+)