| Message ID | 20240301183219.2424889-5-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement FEAT_ECV (Enhanced Counter Virtualization) | expand |
On 3/1/24 08:32, Peter Maydell wrote: > Don't allow the guest to write CNTHCTL_EL2 bits which don't exist. > This is not strictly architecturally required, but it is how we've > tended to implement registers more recently. > > In particular, bits [19:18] are only present with FEAT_RME, > and bits [17:12] will only be present with FEAT_ECV. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > target/arm/helper.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/helper.c b/target/arm/helper.c index 1c82d12a883..8ec61c12440 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2968,6 +2968,24 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, { ARMCPU *cpu = env_archcpu(env); uint32_t oldval = env->cp15.cnthctl_el2; + uint32_t valid_mask = + R_CNTHCTL_EL0PCTEN_MASK | + R_CNTHCTL_EL0VCTEN_MASK | + R_CNTHCTL_EVNTEN_MASK | + R_CNTHCTL_EVNTDIR_MASK | + R_CNTHCTL_EVNTI_MASK | + R_CNTHCTL_EL0VTEN_MASK | + R_CNTHCTL_EL0PTEN_MASK | + R_CNTHCTL_EL1PCTEN_MASK | + R_CNTHCTL_EL1PTEN_MASK; + + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK; + } + + /* Clear RES0 bits */ + value &= valid_mask; + raw_write(env, ri, value); if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
Don't allow the guest to write CNTHCTL_EL2 bits which don't exist. This is not strictly architecturally required, but it is how we've tended to implement registers more recently. In particular, bits [19:18] are only present with FEAT_RME, and bits [17:12] will only be present with FEAT_ECV. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)