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Wed, 7 Feb 2024 16:09:02 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 91E3620043; Wed, 7 Feb 2024 16:09:02 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E672020040; Wed, 7 Feb 2024 16:09:00 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 7 Feb 2024 16:09:00 +0000 (GMT) From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, chalapathi.v@linux.ibm.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v1 5/5] hw/ppc: SPI controller wiring to P10 chip and create seeprom device Date: Wed, 7 Feb 2024 10:08:33 -0600 Message-Id: <20240207160833.3437779-6-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240207160833.3437779-1-chalapathi.v@linux.ibm.com> References: <20240207160833.3437779-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: _lel2OhS-T7y9780jf3vQ_nfE_kjEjZc X-Proofpoint-ORIG-GUID: Lpwku8SpCd3-HJAaiGnk0fGZaXh5rgxm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-07_06,2024-02-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=779 mlxscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402070119 Received-SPF: pass client-ip=148.163.158.5; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This commit creates SPI controller to p10 chip and create the keystore seeprom device on spi_bus2 of PIB_SPIC[2]. Signed-off-by: Chalapathi V --- include/hw/ppc/pnv_chip.h | 4 ++++ hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 0ab5c42308..0d67516ede 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -4,6 +4,8 @@ #include "hw/pci-host/pnv_phb4.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_spi_controller.h" +#include "hw/ppc/pnv_spi_seeprom.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_psi.h" @@ -113,6 +115,8 @@ struct Pnv10Chip { PnvOCC occ; PnvSBE sbe; PnvHomer homer; +#define PNV10_CHIP_MAX_PIB_SPIC 6 + PnvSpiController pib_spic[PNV10_CHIP_MAX_PIB_SPIC]; uint32_t nr_quads; PnvQuad *quads; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0297871bdd..8fffd999f6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1691,6 +1691,11 @@ static void pnv_chip_power10_instance_init(Object *obj) for (i = 0; i < pcc->i2c_num_engines; i++) { object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); } + + for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC ; i++) { + object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], + TYPE_PNV_SPI_CONTROLLER); + } } static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) @@ -1879,6 +1884,33 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_SBE_I2C)); } + + /* PIB SPI Controller */ + for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { + object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", + i , &error_fatal); + /* + * The TPM attached SPIC needs to reverse the bit order in each byte + * it sends to the TPM. + */ + if (i == 4) { + object_property_set_bool(OBJECT(&chip10->pib_spic[i]), + "reverse_bits", true, &error_fatal); + } + if (!qdev_realize(DEVICE(&chip10->pib_spic[i]), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + + i * PNV10_XSCOM_PIB_SPIC_SIZE, + &chip10->pib_spic[i].xscom_spic_regs); + } + + /* Primary MEAS/MVPD/Keystore SEEPROM connected to pib_spic[2]*/ + PnvSpiSeeprom *meas_mvpd_ks_p = PNV_SPI_SEEPROM(spi_create_responder( + (&chip10->pib_spic[2])->spi_bus, + TYPE_PNV_SPI_SEEPROM)); + meas_mvpd_ks_p->file = qemu_find_file(QEMU_FILE_TYPE_BIOS, + "sbe_measurement_seeprom.bin.ecc"); } static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)