@@ -1113,6 +1113,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
+ if (tcg_enabled()) {
+ riscv_tcg_cpu_register_vendor_csr(cpu);
+ }
riscv_cpu_register_gdb_regs_for_features(cs);
#ifndef CONFIG_USER_ONLY
@@ -871,6 +871,24 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
}
}
+void riscv_tcg_cpu_register_vendor_csr(RISCVCPU *cpu)
+{
+ static const struct {
+ bool (*guard_func)(const RISCVCPUConfig *);
+ riscv_csr_operations *csr_ops;
+ } vendors[] = {
+ };
+ for (int i = 0; i < ARRAY_SIZE(vendors); ++i) {
+ if (!vendors[i].guard_func(&cpu->cfg)) {
+ continue;
+ }
+ for (size_t j = 0; j < CSR_TABLE_SIZE &&
+ vendors[i].csr_ops[j].name; j++) {
+ csr_ops[j] = vendors[i].csr_ops[j];
+ }
+ }
+}
+
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
@@ -25,5 +25,6 @@
void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
+void riscv_tcg_cpu_register_vendor_csr(RISCVCPU *cpu);
#endif
riscv specification allows custom CSRs in decode area. So we should register all vendor CSRs in cpu realize stage. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> --- 1) Use int index to quiet the Werror for "i < 0". --- target/riscv/cpu.c | 3 +++ target/riscv/tcg/tcg-cpu.c | 18 ++++++++++++++++++ target/riscv/tcg/tcg-cpu.h | 1 + 3 files changed, 22 insertions(+)