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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id ll5-20020a170907190500b00a36fe6fe976sm579722ejc.190.2024.02.02.02.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 02:14:57 -0800 (PST) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v7 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Date: Fri, 2 Feb 2024 10:14:36 +0000 Message-Id: <20240202101439.3714106-4-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202101439.3714106-1-me@deliversmonkey.space> References: <20240202101439.3714106-1-me@deliversmonkey.space> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 +++ target/riscv/cpu_helper.c | 58 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4c0d7142a5..23a166a91f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -699,6 +699,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, bool riscv_cpu_is_32bit(RISCVCPU *cpu); +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +int riscv_pm_get_pmlen(RISCVPmPmm pmm); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index aedd5bef50..bef7917668 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -142,6 +142,64 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, *pflags = flags; } +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) +{ + int pmm = 0; +#ifndef CONFIG_USER_ONLY + int priv_mode = cpu_address_mode(env); + /* Get current PMM field */ + switch (priv_mode) { + case PRV_M: + pmm = riscv_cpu_cfg(env)->ext_smmpm ? + get_field(env->mseccfg, MSECCFG_PMM) : PMM_FIELD_DISABLED; + break; + case PRV_S: + pmm = riscv_cpu_cfg(env)->ext_smnpm ? + get_field(env->menvcfg, MENVCFG_PMM) : PMM_FIELD_DISABLED; + break; + case PRV_U: + pmm = riscv_cpu_cfg(env)->ext_ssnpm ? + get_field(env->senvcfg, SENVCFG_PMM) : PMM_FIELD_DISABLED; + break; + default: + g_assert_not_reached(); + } +#endif + return pmm; +} + +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) +{ + bool virt_mem_en = false; +#ifndef CONFIG_USER_ONLY + int satp_mode = 0; + int priv_mode = cpu_address_mode(env); + /* Get current PMM field */ + if (riscv_cpu_mxl(env) == MXL_RV32) { + satp_mode = get_field(env->satp, SATP32_MODE); + } else { + satp_mode = get_field(env->satp, SATP64_MODE); + } + virt_mem_en = ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M)); +#endif + return virt_mem_en; +} + +int riscv_pm_get_pmlen(RISCVPmPmm pmm) +{ + switch (pmm) { + case PMM_FIELD_DISABLED: + return 0; + case PMM_FIELD_PMLEN7: + return 7; + case PMM_FIELD_PMLEN16: + return 16; + default: + g_assert_not_reached(); + } + return -1; +} + #ifndef CONFIG_USER_ONLY /*