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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id h2-20020aa79f42000000b006dab0d72cd0sm715111pfr.214.2024.02.01.21.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 21:51:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Alistair Francis , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PULL 22/57] target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index Date: Fri, 2 Feb 2024 15:50:01 +1000 Message-Id: <20240202055036.684176-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240202055036.684176-1-richard.henderson@linaro.org> References: <20240202055036.684176-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu_helper.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f3955c38d..9c825c7b51 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,7 +498,7 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -507,7 +507,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); -#define cpu_mmu_index riscv_cpu_mmu_index +#define cpu_mmu_index riscv_env_mmu_index #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..15f87ecdb0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -33,7 +33,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0;