| Message ID | 20240118074749.2299959-1-rayhan.faizel@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] hw/char/imx_serial: Implement receive FIFO and ageing timer for imx serial. | expand |
On Thu, 18 Jan 2024 at 07:49, Rayhan Faizel <rayhan.faizel@gmail.com> wrote: > > This patch implements a 32 half word FIFO as per imx serial device > specifications. If a non empty FIFO is below the trigger level, an ageing > timer will tick for a duration of 8 characters. On expiry, AGTIM will be set > triggering an interrupt. AGTIM timer resets when there is activity in > the receive FIFO. > > Otherwise, RRDY is set when trigger level is > exceeded. The receive trigger level is 8 in newer kernel versions and 1 in > older ones. > > This change will break migration compatibility. > > [Changes in v3] > > - Caught more whitespace changes that went overlooked > - Moved fifo and timer initialization to realize > > [Changes in v2] > > As per Peter Maydell's suggestions, > > - Use generic FIFO32 implementation in place of handmade impl. > - Moved timer_init to serial init and use timer_del in reset > - Removed stray whitespaces > - Increment VMSTATE version > > Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> > --- > hw/char/imx_serial.c | 97 +++++++++++++++++++++++++++++++----- > include/hw/char/imx_serial.h | 18 ++++++- > 2 files changed, 102 insertions(+), 13 deletions(-) Thanks; this looks good and was easy to review. I have a couple of comments about corner cases of the device behaviour and a few final coding style nits, and that's all. > +static void imx_serial_rx_fifo_push(IMXSerialState *s, uint32_t value) > +{ > + if (fifo32_is_full(&s->rx_fifo)) { > + /* Discard lost character on overflow */ > + fifo32_pop(&s->rx_fifo); Is this the right behaviour on rx overflow? The imx6 TRM I have says the behaviour is: * when we put the 32nd character into the RX FIFO (i.e. the last one which will fit) then we we need to arrange that when it is read it has the URXD.OVRRUN and URXD.ERR bits associated with it, which we can achieve by ORing them in before we push the char into the FIFO here * when the 33rd character arrives, we set USR2.ORE and discard this 33rd character (i.e. never put it in the fifo) > + } > + fifo32_push(&s->rx_fifo, value); > +} > + > +static uint32_t imx_serial_rx_fifo_pop(IMXSerialState *s) > +{ > + if (fifo32_is_empty(&s->rx_fifo)) { > + return URXD_ERR; Similarly, I don't think this is how the UART signals that you just tried to read from an empty FIFO either. My reading of the TRM is that if there's data in the FIFO you get it in the low 8 bits, and CHARRDY is set in bit 15. If the FIFO is empty and the guest tries to read it then it gets a word with CHARRDY clear and the other bits don't have valid data (an entirely 0 word would do). The ERR bit is only set for the OVRRUN/FRMERR/BRK/PRERR cases. > + } > + return fifo32_pop(&s->rx_fifo); > +} > + > +static void imx_serial_rx_fifo_ageing_timer_int(void *opaque) > +{ > + IMXSerialState *s = (IMXSerialState *) opaque; > + s->usr1 |= USR1_AGTIM; > + > + imx_update(s); > +} > + > +static void imx_serial_rx_fifo_ageing_timer_restart(void *opaque) > +{ > + /* > + * Ageing timer starts ticking when > + * RX FIFO is non empty and below trigger level. > + * Timer is reset if new character is received or > + * a FIFO read occurs. > + * Timer triggers an interrupt when duration of > + * 8 characters has passed ( assuming 115200 baudrate ). We don't need the spaces after ( and before ) here. > + */ > + IMXSerialState *s = (IMXSerialState *) opaque; > + uint8_t rxtl = s->ufcr & TL_MASK; > + int rx_used = fifo32_num_used(&s->rx_fifo); > + > + if (rx_used > 0 && rx_used < rxtl) { Rather than checking rx_used against rxtl, can we do what the datasheet says and check against "is USR1.RRDY == 0" ? > + timer_mod_ns(&s->ageing_timer, > + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + AGE_DURATION_NS); > + } else { > + timer_del(&s->ageing_timer); > + } > +} > + > static void imx_serial_reset(IMXSerialState *s) > { > @@ -345,6 +414,10 @@ static void imx_serial_realize(DeviceState *dev, Error **errp) > { > IMXSerialState *s = IMX_SERIAL(dev); > > + fifo32_create(&s->rx_fifo, FIFO_SIZE); > + timer_init_ns(&s->ageing_timer, QEMU_CLOCK_VIRTUAL, > + imx_serial_rx_fifo_ageing_timer_int, s); Generally for indent on function calls we make the second line line up with the first character after the '(' on the preceding line. > + > DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); > > qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, > diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h > index b823f94519..b5f714add1 100644 > --- a/include/hw/char/imx_serial.h > +++ b/include/hw/char/imx_serial.h > @@ -21,10 +21,13 @@ > #include "hw/sysbus.h" > #include "chardev/char-fe.h" > #include "qom/object.h" > +#include "qemu/fifo32.h" > > #define TYPE_IMX_SERIAL "imx.serial" > OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) > > +#define FIFO_SIZE 32 > + > #define URXD_CHARRDY (1<<15) /* character read is valid */ > #define URXD_ERR (1<<14) /* Character has error */ > #define URXD_FRMERR (1<<12) /* Character has frame error */ > @@ -65,6 +68,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) > #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ > #define UCR1_UARTEN (1<<0) /* UART Enable */ > > +#define UCR2_ATEN BIT(3) /* Ageing Timer Enable */ Can you define this as (1<<3), for consistency with how all the other defines in this file are written, please? > #define UCR2_TXEN (1<<2) /* Transmitter enable */ > #define UCR2_RXEN (1<<1) /* Receiver enable */ > #define UCR2_SRST (1<<0) /* Reset complete */ thanks -- PMM
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 1df862eb7f..893e84ccf6 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -26,6 +26,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qemu/fifo32.h" #ifndef DEBUG_IMX_UART #define DEBUG_IMX_UART 0 @@ -41,10 +42,11 @@ static const VMStateDescription vmstate_imx_serial = { .name = TYPE_IMX_SERIAL, - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (const VMStateField[]) { - VMSTATE_INT32(readbuff, IMXSerialState), + VMSTATE_FIFO32(rx_fifo, IMXSerialState), + VMSTATE_TIMER(ageing_timer, IMXSerialState), VMSTATE_UINT32(usr1, IMXSerialState), VMSTATE_UINT32(usr2, IMXSerialState), VMSTATE_UINT32(ucr1, IMXSerialState), @@ -71,6 +73,10 @@ static void imx_update(IMXSerialState *s) * following: */ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); + /* + * Interrupt if AGTIM is set (ageing timer interrupt in RxFIFO) + */ + usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0; /* * Bits that we want in USR2 are not as conveniently laid out, * unfortunately. @@ -87,6 +93,53 @@ static void imx_update(IMXSerialState *s) qemu_set_irq(s->irq, usr1 || usr2); } +static void imx_serial_rx_fifo_push(IMXSerialState *s, uint32_t value) +{ + if (fifo32_is_full(&s->rx_fifo)) { + /* Discard lost character on overflow */ + fifo32_pop(&s->rx_fifo); + } + fifo32_push(&s->rx_fifo, value); +} + +static uint32_t imx_serial_rx_fifo_pop(IMXSerialState *s) +{ + if (fifo32_is_empty(&s->rx_fifo)) { + return URXD_ERR; + } + return fifo32_pop(&s->rx_fifo); +} + +static void imx_serial_rx_fifo_ageing_timer_int(void *opaque) +{ + IMXSerialState *s = (IMXSerialState *) opaque; + s->usr1 |= USR1_AGTIM; + + imx_update(s); +} + +static void imx_serial_rx_fifo_ageing_timer_restart(void *opaque) +{ + /* + * Ageing timer starts ticking when + * RX FIFO is non empty and below trigger level. + * Timer is reset if new character is received or + * a FIFO read occurs. + * Timer triggers an interrupt when duration of + * 8 characters has passed ( assuming 115200 baudrate ). + */ + IMXSerialState *s = (IMXSerialState *) opaque; + uint8_t rxtl = s->ufcr & TL_MASK; + int rx_used = fifo32_num_used(&s->rx_fifo); + + if (rx_used > 0 && rx_used < rxtl) { + timer_mod_ns(&s->ageing_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + AGE_DURATION_NS); + } else { + timer_del(&s->ageing_timer); + } +} + static void imx_serial_reset(IMXSerialState *s) { @@ -102,7 +155,9 @@ static void imx_serial_reset(IMXSerialState *s) s->ucr3 = 0x700; s->ubmr = 0; s->ubrc = 4; - s->readbuff = URXD_ERR; + + fifo32_reset(&s->rx_fifo); + timer_del(&s->ageing_timer); } static void imx_serial_reset_at_boot(DeviceState *dev) @@ -125,20 +180,28 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, unsigned size) { IMXSerialState *s = (IMXSerialState *)opaque; - uint32_t c; + uint32_t c, rx_used; + uint8_t rxtl = s->ufcr & TL_MASK; DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); switch (offset >> 2) { case 0x0: /* URXD */ - c = s->readbuff; + c = imx_serial_rx_fifo_pop(s); if (!(s->uts1 & UTS1_RXEMPTY)) { /* Character is valid */ c |= URXD_CHARRDY; - s->usr1 &= ~USR1_RRDY; - s->usr2 &= ~USR2_RDR; - s->uts1 |= UTS1_RXEMPTY; + rx_used = fifo32_num_used(&s->rx_fifo); + /* Clear RRDY if below threshold */ + if (rx_used < rxtl) { + s->usr1 &= ~USR1_RRDY; + } + if (rx_used == 0) { + s->usr2 &= ~USR2_RDR; + s->uts1 |= UTS1_RXEMPTY; + } imx_update(s); + imx_serial_rx_fifo_ageing_timer_restart(s); qemu_chr_fe_accept_input(&s->chr); } return c; @@ -300,19 +363,25 @@ static void imx_serial_write(void *opaque, hwaddr offset, static int imx_can_receive(void *opaque) { IMXSerialState *s = (IMXSerialState *)opaque; - return !(s->usr1 & USR1_RRDY); + return s->ucr1 & UCR1_RRDYEN && + s->ucr2 & UCR2_RXEN && fifo32_num_used(&s->rx_fifo) < FIFO_SIZE; } static void imx_put_data(void *opaque, uint32_t value) { IMXSerialState *s = (IMXSerialState *)opaque; + uint8_t rxtl = s->ufcr & TL_MASK; DPRINTF("received char\n"); + imx_serial_rx_fifo_push(s, value); + if (fifo32_num_used(&s->rx_fifo) >= rxtl) { + s->usr1 |= USR1_RRDY; + } + + imx_serial_rx_fifo_ageing_timer_restart(s); - s->usr1 |= USR1_RRDY; s->usr2 |= USR2_RDR; s->uts1 &= ~UTS1_RXEMPTY; - s->readbuff = value; if (value & URXD_BRK) { s->usr2 |= USR2_BRCD; } @@ -345,6 +414,10 @@ static void imx_serial_realize(DeviceState *dev, Error **errp) { IMXSerialState *s = IMX_SERIAL(dev); + fifo32_create(&s->rx_fifo, FIFO_SIZE); + timer_init_ns(&s->ageing_timer, QEMU_CLOCK_VIRTUAL, + imx_serial_rx_fifo_ageing_timer_int, s); + DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index b823f94519..b5f714add1 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -21,10 +21,13 @@ #include "hw/sysbus.h" #include "chardev/char-fe.h" #include "qom/object.h" +#include "qemu/fifo32.h" #define TYPE_IMX_SERIAL "imx.serial" OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) +#define FIFO_SIZE 32 + #define URXD_CHARRDY (1<<15) /* character read is valid */ #define URXD_ERR (1<<14) /* Character has error */ #define URXD_FRMERR (1<<12) /* Character has frame error */ @@ -65,6 +68,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ #define UCR1_UARTEN (1<<0) /* UART Enable */ +#define UCR2_ATEN BIT(3) /* Ageing Timer Enable */ #define UCR2_TXEN (1<<2) /* Transmitter enable */ #define UCR2_RXEN (1<<1) /* Receiver enable */ #define UCR2_SRST (1<<0) /* Reset complete */ @@ -78,13 +82,25 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) #define UTS1_TXFULL (1<<4) #define UTS1_RXFULL (1<<3) +#define TL_MASK 0x3f + + /* Bit time in nanoseconds assuming maximum baud rate of 115200 */ +#define BIT_TIME_NS 8681 + +/* Assume 8 bits per character */ +#define NUM_BITS 8 + +/* Ageing timer triggers after 8 characters */ +#define AGE_DURATION_NS (8 * NUM_BITS * BIT_TIME_NS) + struct IMXSerialState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ MemoryRegion iomem; - int32_t readbuff; + QEMUTimer ageing_timer; + Fifo32 rx_fifo; uint32_t usr1; uint32_t usr2;
This patch implements a 32 half word FIFO as per imx serial device specifications. If a non empty FIFO is below the trigger level, an ageing timer will tick for a duration of 8 characters. On expiry, AGTIM will be set triggering an interrupt. AGTIM timer resets when there is activity in the receive FIFO. Otherwise, RRDY is set when trigger level is exceeded. The receive trigger level is 8 in newer kernel versions and 1 in older ones. This change will break migration compatibility. [Changes in v3] - Caught more whitespace changes that went overlooked - Moved fifo and timer initialization to realize [Changes in v2] As per Peter Maydell's suggestions, - Use generic FIFO32 implementation in place of handmade impl. - Moved timer_init to serial init and use timer_del in reset - Removed stray whitespaces - Increment VMSTATE version Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> --- hw/char/imx_serial.c | 97 +++++++++++++++++++++++++++++++----- include/hw/char/imx_serial.h | 18 ++++++- 2 files changed, 102 insertions(+), 13 deletions(-)