diff mbox series

[08/13] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)

Message ID 20240112213812.173521-9-dbarboza@ventanamicro.com
State New
Headers show
Series target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' | expand

Commit Message

Daniel Henrique Barboza Jan. 12, 2024, 9:38 p.m. UTC 
Use the new 'vlenb' CPU config to validate fractional LMUL. The original
comparison is done with 'vlen' and 'sew', both in bits. Use sew/8, or
sew in bytes, to do a direct comparison with vlenb.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/vector_helper.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Richard Henderson Jan. 12, 2024, 10:40 p.m. UTC | #1 
On 1/13/24 08:38, Daniel Henrique Barboza wrote:
> Use the new 'vlenb' CPU config to validate fractional LMUL. The original
> comparison is done with 'vlen' and 'sew', both in bits. Use sew/8, or
> sew in bytes, to do a direct comparison with vlenb.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>   target/riscv/vector_helper.c | 9 ++++++---
>   1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index cb944229b0..0c1a485d1e 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -45,9 +45,12 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>                                               xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>   
>       if (lmul & 4) {
> -        /* Fractional LMUL - check LMUL * VLEN >= SEW */
> -        if (lmul == 4 ||
> -            cpu->cfg.vlen >> (8 - lmul) < sew) {
> +        /*
> +         * Fractional LMUL - check LMUL * VLEN >= SEW, or
> +         * vlen >> (8 - lmul) < sew. We have 'vlenb', so
> +         * compare it with sew in bytes.
> +         */
> +        if (lmul == 4 || cpu->cfg.vlenb >> (8 - lmul) < (sew << 3)) {

You're shifting sew the wrong direction.  But better to simply adjust the vlenb shift:

- cpu->cfg.vlen >> (8 - lmul) < sew
+ cpu->cfg.vlenb >> (8 - 3 - lmul) < sew


r~
diff mbox series

Patch

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cb944229b0..0c1a485d1e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -45,9 +45,12 @@  target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
 
     if (lmul & 4) {
-        /* Fractional LMUL - check LMUL * VLEN >= SEW */
-        if (lmul == 4 ||
-            cpu->cfg.vlen >> (8 - lmul) < sew) {
+        /*
+         * Fractional LMUL - check LMUL * VLEN >= SEW, or
+         * vlen >> (8 - lmul) < sew. We have 'vlenb', so
+         * compare it with sew in bytes.
+         */
+        if (lmul == 4 || cpu->cfg.vlenb >> (8 - lmul) < (sew << 3)) {
             vill = true;
         }
     }