diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index a3e18bb3d7..f9d848171f 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -1133,14 +1133,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) switch (saddr) { case ESP_FIFO: - if (s->dma_memory_read && s->dma_memory_write && - (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { - /* Data out. */ - qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); - s->rregs[ESP_FIFO] = 0; - } else { - s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); - } + s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); val = s->rregs[ESP_FIFO]; break; case ESP_RINTR:
The latest state machines can handle mixing DMA and non-DMA FIFO access for all SCSI phases except DATA IN and DATA OUT. For DATA IN and DATA OUT phases, the transfer is complete when TC == 0 and the updated logic will now handle TC underflow correctly, which makes it just about impossible to manually manipulate the FIFO during a DMA transfer. Remove the restriction on FIFO read access when DMA memory routines are defined which also allows the NeXTCube machine to pass its self-test. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> --- hw/scsi/esp.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-)