Message ID | 20240103084900.22856-3-shentey@gmail.com |
---|---|
State | New |
Headers | show |
Series | Fix PIC interrupt handling of x86 CPUs if APIC is globally disabled | expand |
Bernhard Beschow <shentey@gmail.com> writes: > Signed-off-by: Bernhard Beschow <shentey@gmail.com> > --- > target/i386/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 95d5f16cd5..2ae271e9a1 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -2179,7 +2179,7 @@ static const CPUCaches epyc_genoa_cache_info = { > * Conceal VM entries from PT > * Enable ENCLS exiting > * Mode-based execute control (XS/XU) > - s TSC scaling (Skylake Server and newer) > + * TSC scaling (Skylake Server and newer) > * GPA translation for PT (IceLake and newer) > * User wait and pause > * ENCLV exiting Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 95d5f16cd5..2ae271e9a1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2179,7 +2179,7 @@ static const CPUCaches epyc_genoa_cache_info = { * Conceal VM entries from PT * Enable ENCLS exiting * Mode-based execute control (XS/XU) - s TSC scaling (Skylake Server and newer) + * TSC scaling (Skylake Server and newer) * GPA translation for PT (IceLake and newer) * User wait and pause * ENCLV exiting
Signed-off-by: Bernhard Beschow <shentey@gmail.com> --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)