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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 28/33] hw/arm/vexpress: Let the A9/A15MPcore create/wire the CPU cores Date: Tue, 12 Dec 2023 17:29:28 +0100 Message-ID: <20231212162935.42910-29-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the properties on the mpcore object to let it create and wire the CPU cores. Remove the redundant code. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/vexpress.c | 51 ++++++----------------------------------------- 1 file changed, 6 insertions(+), 45 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 294b6f15f2..c104759588 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -210,45 +210,19 @@ static void init_cpus(MachineState *ms, const char *cpu_type, qemu_irq *pic, bool secure, bool virt) { DeviceState *dev; - SysBusDevice *busdev; - int n; - unsigned int smp_cpus = ms->smp.cpus; - /* Create the actual CPUs */ - for (n = 0; n < smp_cpus; n++) { - Object *cpuobj = object_new(cpu_type); - - if (!secure) { - object_property_set_bool(cpuobj, "has_el3", false, NULL); - } - if (!virt) { - if (object_property_find(cpuobj, "has_el2")) { - object_property_set_bool(cpuobj, "has_el2", false, NULL); - } - } - - if (object_property_find(cpuobj, "reset-cbar")) { - object_property_set_int(cpuobj, "reset-cbar", periphbase, - &error_abort); - } - qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); - } - - /* Create the private peripheral devices (including the GIC); - * this must happen after the CPUs are created because a15mpcore_priv - * wires itself up to the CPU's generic_timer gpio out lines. - */ dev = qdev_new(privdev); + qdev_prop_set_uint32(dev, "num-cores", ms->smp.cpus); + qdev_prop_set_string(dev, "cpu-type", cpu_type); if (!secure) { qdev_prop_set_bit(dev, "cpu-has-el3", false); } if (!virt) { qdev_prop_set_bit(dev, "cpu-has-el2", false); } - qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); - busdev = SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(busdev, &error_fatal); - sysbus_mmio_map(busdev, 0, periphbase); + qdev_prop_set_uint64(dev, "cpu-reset-cbar", periphbase); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, periphbase); /* Interrupts [42:0] are from the motherboard; * [47:43] are reserved; [63:48] are daughterboard @@ -256,22 +230,9 @@ static void init_cpus(MachineState *ms, const char *cpu_type, * external interrupts starting from 32 (because there * are internal interrupts 0..31). */ - for (n = 0; n < 64; n++) { + for (int n = 0; n < 64; n++) { pic[n] = qdev_get_gpio_in(dev, n); } - - /* Connect the CPUs to the GIC */ - for (n = 0; n < smp_cpus; n++) { - DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); - - sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); - sysbus_connect_irq(busdev, n + smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); - sysbus_connect_irq(busdev, n + 2 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); - sysbus_connect_irq(busdev, n + 3 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); - } } static void a9_daughterboard_init(VexpressMachineState *vms,