From patchwork Fri Dec 8 02:31:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Kambalin X-Patchwork-Id: 1873608 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=G2oCh4To; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Smb3J0RzVz23nW for ; Fri, 8 Dec 2023 13:40:28 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rBQfW-0004EN-Ne; Thu, 07 Dec 2023 21:32:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rBQfV-0004DQ-5e; Thu, 07 Dec 2023 21:32:45 -0500 Received: from mail-lj1-x233.google.com ([2a00:1450:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rBQfT-0002U2-AB; Thu, 07 Dec 2023 21:32:44 -0500 Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c9f85eff28so22522041fa.3; Thu, 07 Dec 2023 18:32:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702002761; x=1702607561; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wFeuloyQQG/pWB1qNvNMADuHoBFz7/WggqgaHUnwlWg=; b=G2oCh4ToxtDpx4+0ClPou+/gYHZTqZkyK8sikUkdjXQr0wPS14fx5fBQbqfkImnv6D RyCfi1Eu6lSaTABAQ3QgR77I0ShLCpP4QC6Lbkl/5hHfz0AyOScnY3dhvfhll2zCPYVc Vt/1TLQSb9xfq7U+17gvgRmtJP6dcAZQCHKqlvhMMu5WxOFaMk5coOx6ksP5JBTa2YPd THUWEY6f6GggPPIJ0cgvvRU9mZL57Xs0NiiYDq81XUOBlCiapVJ91rzwxe9kYibw0zDl rHew1bR4x0HJCwk+J9H4WEtcO+oFjFytduQ8hzuClCU5eFeZvvMBjJq4Zd/Db7Ml+OZQ NoGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702002761; x=1702607561; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wFeuloyQQG/pWB1qNvNMADuHoBFz7/WggqgaHUnwlWg=; b=SfUAzHRTGMQPqZdc/nvndHfSUCGRXyjESqg2Wt0JEiBppDQvL9XrN6Ok++l3CHo+So x2i4Xkkf2R/85hxTdMcantcbZGrijs2rR4Nkxg5MSEz50ju/C7iMkU5tG+Hf0+h0Wk+X /ZyPn0IP9TEAvSOG6LK8M1YHVuF5Cea3Xw8c7F6XRN0yOBC7J2dFztnuIGpvsr6ZyPFi eRgI+BVbmPeU9kKeIXVEnJ+HLXWRjEPWEejvwtB04Yk/lncrF+0cPcPgHALmlr+f7FUi dzqZJCAgFaoZ0suXWBXjCYgMdMl6mcjrRId8p+n2Nr1NzCGu7kXOVqctJr+IeO+D7gXS yfsA== X-Gm-Message-State: AOJu0YzZxLuPETIAKi2FpjyPWi/IiENISN/DFHXUqju3apt0uaC53i6d bsEsgoS54fEGAijzVwoLmbAUtMcacmYqmA== X-Google-Smtp-Source: AGHT+IG29kbvMS0AkfX3vEhWq6wVJ6EV/T5CGgF6cvX17/10Xs061AJIdlt6qKauybwDbWBQaHXKbw== X-Received: by 2002:a2e:80c4:0:b0:2ca:1bf:dc7e with SMTP id r4-20020a2e80c4000000b002ca01bfdc7emr1941413ljg.77.1702002760943; Thu, 07 Dec 2023 18:32:40 -0800 (PST) Received: from localhost.localdomain ([185.200.240.39]) by smtp.gmail.com with ESMTPSA id r1-20020a2e94c1000000b002c9e6cbf78esm99062ljh.19.2023.12.07.18.32.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 18:32:40 -0800 (PST) From: Sergey Kambalin X-Google-Original-From: Sergey Kambalin To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Sergey Kambalin Subject: [PATCH v4 14/45] Add BCM2838 PCIE Root Complex Date: Thu, 7 Dec 2023 20:31:14 -0600 Message-Id: <20231208023145.1385775-15-sergey.kambalin@auriga.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231208023145.1385775-1-sergey.kambalin@auriga.com> References: <20231208023145.1385775-1-sergey.kambalin@auriga.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=serg.oker@gmail.com; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Sergey Kambalin --- hw/arm/bcm2838_pcie.c | 74 +++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 5 ++- hw/arm/trace-events | 4 ++ include/hw/arm/bcm2838_pcie.h | 53 +++++++++++++++++++++++++ 4 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 hw/arm/bcm2838_pcie.c create mode 100644 include/hw/arm/bcm2838_pcie.h diff --git a/hw/arm/bcm2838_pcie.c b/hw/arm/bcm2838_pcie.c new file mode 100644 index 0000000000..3b4373c6a6 --- /dev/null +++ b/hw/arm/bcm2838_pcie.c @@ -0,0 +1,74 @@ +/* + * BCM2838 PCIe Root Complex emulation + * + * Copyright (C) 2022 Ovchinnikov Vitalii + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/irq.h" +#include "hw/pci-host/gpex.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "qemu/module.h" +#include "hw/arm/bcm2838_pcie.h" +#include "trace.h" + +/* + * RC root part (D0:F0) + */ + +static void bcm2838_pcie_root_reg_reset(PCIDevice *dev) +{ + BCM2838PcieRootState *s = BCM2838_PCIE_ROOT(dev); + memset(s->regs, 0xFF, sizeof(s->regs)); +} + +static void bcm2838_pcie_root_realize(PCIDevice *dev, Error **errp) { + bcm2838_pcie_root_reg_reset(dev); +} + +static void bcm2838_pcie_root_init(Object *obj) +{ + PCIBridge *br = PCI_BRIDGE(obj); + br->bus_name = "pcie.1"; +} + +static void bcm2838_pcie_root_class_init(ObjectClass *class, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(class); + PCIDeviceClass *k = PCI_DEVICE_CLASS(class); + BCM2838PcieRootClass *brpc = BCM2838_PCIE_ROOT_CLASS(class); + + dc->desc = "BCM2711 PCIe Bridge"; + /* + * PCI-facing part of the host bridge, not usable without the host-facing + * part, which can't be device_add'ed. + */ + dc->user_creatable = false; + k->vendor_id = BCM2838_PCIE_VENDOR_ID; + k->device_id = BCM2838_PCIE_DEVICE_ID; + k->revision = BCM2838_PCIE_REVISION; + brpc->parent_obj.exp_offset = BCM2838_PCIE_EXP_CAP_OFFSET; + brpc->parent_obj.aer_offset = BCM2838_PCIE_AER_CAP_OFFSET; + brpc->parent_realize = k->realize; + k->realize = bcm2838_pcie_root_realize; +} + +static const TypeInfo bcm2838_pcie_root_info = { + .name = TYPE_BCM2838_PCIE_ROOT, + .parent = TYPE_PCIE_ROOT_PORT, + .instance_size = sizeof(BCM2838PcieRootState), + .instance_init = bcm2838_pcie_root_init, + .class_init = bcm2838_pcie_root_class_init, +}; + +static void bcm2838_pcie_register(void) +{ + type_register_static(&bcm2838_pcie_root_info); +} + +type_init(bcm2838_pcie_register) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 27e6797de2..b26ed13c6f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,7 +39,10 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubi arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) -arm_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) +arm_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files( + 'bcm2838.c', + 'bcm2838_pcie.c', + 'raspi4b.c')) arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 4f0167e638..6cfab31539 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -55,5 +55,9 @@ smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64 +# bcm2838_pcie.c +bcm2838_pcie_host_read(unsigned int size, uint64_t offset, uint64_t value) "%u bytes @ 0x%04"PRIx64": 0x%016"PRIx64 +bcm2838_pcie_host_write(unsigned int size, uint64_t offset, uint64_t value) "%u bytes @ 0x%04"PRIx64": 0x%016"PRIx64 + # bcm2838.c bcm2838_gic_set_irq(int irq, int level) "gic irq:%d lvl:%d" diff --git a/include/hw/arm/bcm2838_pcie.h b/include/hw/arm/bcm2838_pcie.h new file mode 100644 index 0000000000..39828f817f --- /dev/null +++ b/include/hw/arm/bcm2838_pcie.h @@ -0,0 +1,53 @@ +/* + * BCM2838 PCIe Root Complex emulation + * + * Copyright (C) 2022 Ovchinnikov Vitalii + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef BCM2838_PCIE_H +#define BCM2838_PCIE_H + +#include "exec/hwaddr.h" +#include "hw/sysbus.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie_host.h" +#include "hw/pci/pcie_port.h" +#include "qom/object.h" + +#define TYPE_BCM2838_PCIE_ROOT "bcm2838-pcie-root" +OBJECT_DECLARE_TYPE(BCM2838PcieRootState, BCM2838PcieRootClass, + BCM2838_PCIE_ROOT) + +#define BCM2838_PCIE_VENDOR_ID 0x14E4 +#define BCM2838_PCIE_DEVICE_ID 0x2711 +#define BCM2838_PCIE_REVISION 20 + +#define BCM2838_PCIE_REGS_SIZE 0x9310 +#define BCM2838_PCIE_NUM_IRQS 4 + +#define BCM2838_PCIE_EXP_CAP_OFFSET 0xAC +#define BCM2838_PCIE_AER_CAP_OFFSET 0x100 + +#define BCM2838_PCIE_EXT_CFG_DATA 0x8000 +#define BCM2838_PCIE_EXT_CFG_INDEX 0x9000 + +struct BCM2838PcieRootState { + /*< private >*/ + PCIESlot parent_obj; + + /*< public >*/ + uint8_t regs[BCM2838_PCIE_REGS_SIZE - PCIE_CONFIG_SPACE_SIZE]; +}; + +struct BCM2838PcieRootClass { + /*< private >*/ + PCIERootPortClass parent_obj; + + /*< public >*/ + void (*parent_realize)(PCIDevice *dev, Error **errp); +}; + + +#endif /* BCM2838_PCIE_H */