From patchwork Thu Nov 9 13:59:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 1862105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SR3qb5PTMz1yRF for ; Fri, 10 Nov 2023 01:14:35 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r15hM-0000tw-5d; Thu, 09 Nov 2023 09:07:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r15fC-0004Po-BE; Thu, 09 Nov 2023 09:05:47 -0500 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r15f7-0007lp-W1; Thu, 09 Nov 2023 09:05:40 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id E08BE31BF7; Thu, 9 Nov 2023 16:59:58 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id E9FB83452D; Thu, 9 Nov 2023 16:59:50 +0300 (MSK) Received: (nullmailer pid 1462968 invoked by uid 1000); Thu, 09 Nov 2023 13:59:47 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Niklas Cassel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Kevin Wolf , Michael Tokarev Subject: [Stable-7.2.7 62/62] hw/ide/ahci: trigger either error IRQ or regular IRQ, not both Date: Thu, 9 Nov 2023 16:59:30 +0300 Message-Id: <20231109135933.1462615-62-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Niklas Cassel According to AHCI 1.3.1, 5.3.8.1 RegFIS:Entry, if ERR_STAT is set, we jump to state ERR:FatalTaskfile, which will raise a TFES IRQ unconditionally, regardless if the I bit is set in the FIS or not. Thus, we should never raise a normal IRQ after having sent an error IRQ. NOTE: for QEMU platforms that use SeaBIOS, this patch depends on QEMU commit 784155cdcb02 ("seabios: update submodule to git snapshot"), and QEMU commit 14f5a7bae4cb ("seabios: update binaries to git snapshot"), which update SeaBIOS to a version that contains SeaBIOS commit 1281e340 ("ahci: handle TFES irq correctly"). Signed-off-by: Niklas Cassel Message-ID: <20231011131220.1992064-1-nks@flawful.org> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Kevin Wolf Signed-off-by: Kevin Wolf (cherry picked from commit b523a3d54f3d031a54cd0931cc5d855608e63140) Signed-off-by: Michael Tokarev diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index c5e79b6e6d..73739567ee 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -896,11 +896,10 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i) pr->tfdata = (ad->port.ifs[0].error << 8) | ad->port.ifs[0].status; + /* TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. */ if (d2h_fis[2] & ERR_STAT) { ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); - } - - if (d2h_fis_i) { + } else if (d2h_fis_i) { ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); }