Message ID | 20231102173835.609985-24-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show
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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020adff350000000b003258934a4bcsm3046805wrp.42.2023.11.02.10.38.49 for <qemu-devel@nongnu.org> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 10:38:49 -0700 (PDT) From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 23/33] target/arm: Enable FEAT_MOPS insns in user-mode emulation Date: Thu, 2 Nov 2023 17:38:25 +0000 Message-Id: <20231102173835.609985-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231102173835.609985-1-peter.maydell@linaro.org> References: <20231102173835.609985-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org |
Series |
[PULL,01/33] linux-user/elfload: Add missing arm64 hwcap values
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diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 954328d72a0..df6496b0193 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -296,6 +296,8 @@ static void arm_cpu_reset_hold(Object *obj) env->cp15.sctlr_el[1] |= SCTLR_TSCXT; /* Disable access to Debug Communication Channel (DCC). */ env->cp15.mdscr_el1 |= 1 << 12; + /* Enable FEAT_MOPS */ + env->cp15.sctlr_el[1] |= SCTLR_MSCEN; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) {