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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id v20-20020aa78514000000b006934e7ceb79sm1800230pfn.32.2023.11.01.18.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 18:37:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v3 80/88] target/hppa: Add unwind_breg to CPUHPPAState Date: Wed, 1 Nov 2023 18:30:08 -0700 Message-Id: <20231102013016.369010-81-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231102013016.369010-1-richard.henderson@linaro.org> References: <20231102013016.369010-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 8 +++++++- target/hppa/cpu.c | 1 + target/hppa/translate.c | 13 ++++++++++++- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index ea8e7e99a4..144794d089 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -45,7 +45,7 @@ #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) -#define TARGET_INSN_START_EXTRA_WORDS 1 +#define TARGET_INSN_START_EXTRA_WORDS 2 /* No need to flush MMU_PHYS_IDX */ #define HPPA_MMU_FLUSH_MASK \ @@ -208,6 +208,12 @@ typedef struct CPUArchState { target_ulong cr_back[2]; /* back of cr17/cr18 */ target_ulong shadow[7]; /* shadow registers */ + /* + * During unwind of a memory insn, the base register of the address. + * This is used to construct CR_IOR for pa2.0. + */ + uint32_t unwind_breg; + /* * ??? The number of entries isn't specified by the architecture. * BTLBs are not supported in 64-bit machines. diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e1597ba8a5..04de1689d7 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -80,6 +80,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, if (data[1] != (target_ulong)-1) { cpu->env.iaoq_b = data[1]; } + cpu->env.unwind_breg = data[2]; /* * Since we were executing the instruction at IAOQ_F, and took some * sort of action that provoked the cpu_restore_state, we can infer diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f7621590e4..27846f5ad8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -44,6 +44,7 @@ typedef struct DisasCond { typedef struct DisasContext { DisasContextBase base; CPUState *cs; + TCGOp *insn_start; uint64_t iaoq_f; uint64_t iaoq_b; @@ -234,6 +235,13 @@ void hppa_translate_init(void) "iasq_b"); } +static void set_insn_breg(DisasContext *ctx, int breg) +{ + assert(ctx->insn_start != NULL); + tcg_set_insn_start_param(ctx->insn_start, 2, breg); + ctx->insn_start = NULL; +} + static DisasCond cond_make_f(void) { return (DisasCond){ @@ -1324,6 +1332,8 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, TCGv_i64 ofs; TCGv_i64 addr; + set_insn_breg(ctx, rb); + /* Note that RX is mutually exclusive with DISP. */ if (rx) { ofs = tcg_temp_new_i64(); @@ -4455,7 +4465,8 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); + tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0); + ctx->insn_start = tcg_last_op(); } static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)