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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id z187-20020a2533c4000000b00d9cc49edae9sm329724ybz.63.2023.11.01.13.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 13:42:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v8 04/19] target/riscv/cpu.c: set satp_mode_max MBARE during satp_finalize() Date: Wed, 1 Nov 2023 17:41:49 -0300 Message-ID: <20231101204204.345470-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231101204204.345470-1-dbarboza@ventanamicro.com> References: <20231101204204.345470-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::b2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-yb1-xb2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org KVM CPUs can handle "cpu->cfg.satp_mode.supported == 0" because KVM will make it do internally, not requiring the current SATP support from TCG. But other TCG CPUs doesn't deal well with it. We'll assert out before OpenSBI if the CPU doesn't set a default: ERROR:../target/riscv/cpu.c:317:satp_mode_max_from_map: assertion failed: (map > 0) Bail out! ERROR:../target/riscv/cpu.c:317:satp_mode_max_from_map: assertion failed: (map > 0) This will be thrown by target/riscv/csr.c, write_satp(), when stepping in validate_vm(). There's no current CPUs affected by it, but next patch will add a new CPU that doesn't have defaults and this assert will be hit. Change riscv_cpu_satp_mode_finalize() to set satp_mode_max_supported() to MBARE if the CPU happens to not have a max mode set yet. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f6837ecb7..f7c1989d14 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -942,9 +942,19 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; uint8_t satp_mode_map_max, satp_mode_supported_max; - /* The CPU wants the OS to decide which satp mode to use */ if (cpu->cfg.satp_mode.supported == 0) { - return; + if (kvm_enabled()) { + /* The CPU wants the OS to decide which satp mode to use */ + return; + } + + /* + * We do not handle cpu->cfg.satp_mode.supported == 0 + * with TCG yet. Set to MBARE. + */ + if (tcg_enabled()) { + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); + } } satp_mode_supported_max =