From patchwork Tue Oct 31 20:39:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1857756 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=mqv2GP+t; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SKhq60xzXz1yQ5 for ; Wed, 1 Nov 2023 07:40:34 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qxvWq-0005Ne-Up; Tue, 31 Oct 2023 16:40:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qxvWo-0005ML-NP for qemu-devel@nongnu.org; Tue, 31 Oct 2023 16:39:58 -0400 Received: from mail-yw1-x112c.google.com ([2607:f8b0:4864:20::112c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qxvWn-0007aV-4j for qemu-devel@nongnu.org; Tue, 31 Oct 2023 16:39:58 -0400 Received: by mail-yw1-x112c.google.com with SMTP id 00721157ae682-5af6c445e9eso54009387b3.0 for ; Tue, 31 Oct 2023 13:39:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698784795; x=1699389595; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qNZMARQ8hTLEOWnxe5zMR6aLRLvM68r8c86LCyLas2c=; b=mqv2GP+tYTsEkxi/fhp5pBUIW644/rRou07l2UwB794y/4OZGgTXOV5WnFL5dxXnaH I9mHGfDKj+CJlH6oRlljTV6QkM5LDtmGn41/ED7tfufSO9Y3ztmc61hZKN7ypmrtZMmZ xdyiyTJjPl8rieufO8DVfcAX0yDZa8GSyHWSQShE63rI1R7TrrSRWk/NSZSfrq2nlIqz 929FKc4UEeIm/wYsuyntDeXicB+aXg2Rdclg/Z06rFDgx6cYOkhMjJWLu9EBnhTXXczk Abk7+hSxmtGacjcgHcZSa0VmoAVcfoRj6rQqgRs73F5amZcgyTEPkVb8NpUhnZ6vG9BH TKLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698784795; x=1699389595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qNZMARQ8hTLEOWnxe5zMR6aLRLvM68r8c86LCyLas2c=; b=Y+9JnNee6sFJugeE9/mCWt8mTvSAHX+cD+AKxdAXJ9KbT+bsgcUFhK77N7o/NYrzzF Z5ABCZmyVZB4V08d2XB+lqUsss8F5t4th/Koj675mNmL6IlEDw+agCHf8YoktqhDZxfq eiIVf2FJcRViqPUnWI0jyv/zJ/wJbfVkJx8sHCh6r7R2T96Sr4hHlXNrENNb6xTvxgWx DofMsb45ZcS4mYfPf6AFlg1anfKAVNqIkyVm10msmyCckf87F21LkYlzr/KLlisjmJqC ieijalD44yK1Yk29/vEEQ6B0fBvmbe158grwxMlum4zcZtATYboPnfHSKfE3H7W2EN/V Juig== X-Gm-Message-State: AOJu0YxJYe7khotkh5RmFZ1jza+b6ddzeUs9ea7wC5HRArn07FnaHn8d rB1LsG44/sW8tmyCw+OZn3HmYjoFOHhG5/xAVoo= X-Google-Smtp-Source: AGHT+IEzxfLEPJSaSL/3ET2wjBiyurJFRHRdmSLM9eF/OrxjadhlbSD9hWxoh4vQBeaPX7dm4uiPTA== X-Received: by 2002:a81:cf0b:0:b0:5a7:aa83:9fb with SMTP id u11-20020a81cf0b000000b005a7aa8309fbmr12268337ywi.0.1698784795641; Tue, 31 Oct 2023 13:39:55 -0700 (PDT) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id k1-20020a81ff01000000b005add997ae53sm1272802ywn.81.2023.10.31.13.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 13:39:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v7 11/16] target/riscv/tcg: add riscv_cpu_write_misa_bit() Date: Tue, 31 Oct 2023 17:39:11 -0300 Message-ID: <20231031203916.197332-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231031203916.197332-1-dbarboza@ventanamicro.com> References: <20231031203916.197332-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::112c; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x112c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 44 ++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 70cd07efd7..b62890e568 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } +static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, + bool enabled) +{ + CPURISCVState *env = &cpu->env; + + if (enabled) { + env->misa_ext |= bit; + env->misa_ext_mask |= bit; + } else { + env->misa_ext &= ~bit; + env->misa_ext_mask &= ~bit; + } +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -711,20 +725,14 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, return; } - if (value) { - if (vendor_cpu) { - g_autofree char *cpuname = riscv_cpu_get_name(cpu); - error_setg(errp, "'%s' CPU does not allow enabling extensions", - cpuname); - return; - } - - env->misa_ext |= misa_bit; - env->misa_ext_mask |= misa_bit; - } else { - env->misa_ext &= ~misa_bit; - env->misa_ext_mask &= ~misa_bit; + if (value && vendor_cpu) { + g_autofree char *cpuname = riscv_cpu_get_name(cpu); + error_setg(errp, "'%s' CPU does not allow enabling extensions", + cpuname); + return; } + + riscv_cpu_write_misa_bit(cpu, misa_bit, value); } static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, @@ -768,7 +776,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { - CPURISCVState *env = &RISCV_CPU(cpu_obj)->env; bool use_def_vals = riscv_cpu_is_generic(cpu_obj); int i; @@ -789,13 +796,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - if (misa_cfg->enabled) { - env->misa_ext |= bit; - env->misa_ext_mask |= bit; - } else { - env->misa_ext &= ~bit; - env->misa_ext_mask &= ~bit; - } + riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, + misa_cfg->enabled); } } }