@@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
+ ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
@@ -1375,6 +1376,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
+ MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false),
DEFINE_PROP_END_OF_LIST(),
};
Signed-off-by: Max Chou <max.chou@sifive.com> --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+)